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4 to 11 Decoder in VerilogA

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PaulineVi

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Hi friends! I'm a student and I'm having difficulty with my codes on our 4 to 11 Decoder. This is done in VerilogA code on Cadence. I've experienced this error and dunno what's the problem. Can someone help me fix my codes? Thankyou :)
19415930_1596158860403761_90697403_n.png19427668_1596164647069849_384341172_n.png
 

Thankyou Sir/Ma'am but we get rid of the ';' and there's still an error or marker on the always statement. The marker message says "Error:syntax error."
 

get rid of the ';' typo at the end of the always statement.

Next time post the code within code or syntax tags and don't use screen captures.

- - - Updated - - -

I noticed you are also missing a ':' after the default keyword.

Not having the code in a text window makes this much harder to notice problems in your code. :thumbsdown:

- - - Updated - - -

If you still have problems after fixing the : after default, then post the code like so...

[ code ]
...cut and pasted code
[ /code ]

Note: remove spaces in the code tag lines (spaces added to keep the forum from turning the lines into actual tags).
 

There is still an error on the always statement after adding ":" after the default.

Code: 
// VerilogA for BGR_v2, decoder2, veriloga
`include "constants.vams"
`include "disciplines.vams"
module decoder2 (
	binary_in , // 4 bit binary input
	decoder_out, // 11-bit out
	enable   // enable for the decoder
 	);
input [3:0] binary_in;
input enable;
output [10:0] decoder_out;
electrical binary_in, decoder_out, enable;
//reg [10:0] decoder2_out;
always @(enable or binary_in)
begin
  decoder_out=0;
  if (enable) begin
    case (binary_in)
	 4'h0: decoder_out=11'h0001;
	 4'h1: decoder_out=11'h0002;
	 4'h2: decoder_out=11'h0004;
	 4'h3: decoder_out=11'h0008;
	 4'h4: decoder_out=11'h0010;
	 4'h5: decoder_out=11'h0020;
	 4'h6: decoder_out=11'h0040;
	 4'h7: decoder_out=11'h0080;
	 4'h8: decoder_out=11'h0100;
	 4'h9: decoder_out=11'h0200;
	 4'hA: decoder_out=11'h0400;
	 default: decoder_out=11'h000;
	endcase
   end
  end
 endmodule
 

It must be something specific to Verilog-A. I use regular Verilog for digital design, but syntax wise the always procedural block is correct now.

One thing I do differently is use ',' instead of 'or' in my sensitivity lists. Maybe Verilog-A requires that ',' be used (I have no idea if that is the case). Plain Verilog allows either. Also plain Verilog would require that decoder_out be defined as a reg, but don't know if that is necessary in Verilog-A.
 

Thank you for patiently replying to my inquiry. I tried to use Verilog instead of VerilogA in Cadence but I am experiencing the error below upon saving and checking the codes.
19441411_1596357873717193_1191047214_n.png
 

nothing I can do to help you with that, the system admin, the IT dept, or you will have to find the location of the tools and add that to your path.

BTW, adding the reg declaration and commenting out the electrical line and the includes, the code from above compiles fine using Modelsim/Vivado simulators.
 

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