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How do I simulate a 3 stage Ring Oscillator? [Virtuoso]

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is this the netlist?
Code: 
// Generated for: spectre
// Generated on: Jul  1 20:58:47 2017
// Design library name: patruzecisitrei
// Design cell name: oscilator
// Design view name: schematic
simulator lang=spectre
global 0 vdd!
include "/work/tdk/AMS/H18/4.11/spectre/h18/soac/mcparams.scs"
include "/work/tdk/AMS/H18/4.11/spectre/h18/soac/design.scs" section=noitm
include "/work/tdk/AMS/H18/4.11/spectre/h18/soac/res.scs" section=restm
include "/work/tdk/AMS/H18/4.11/spectre/h18/soac/cap.scs" section=captm
include "/work/tdk/AMS/H18/4.11/spectre/h18/soac/bip.scs" section=biptm
include "/work/tdk/AMS/H18/4.11/spectre/h18/soac/esddi.scs" section=esdditm
include "/work/tdk/AMS/H18/4.11/spectre/h18/soac/cmos53.scs" section=cmostm

// Library name: patruzecisitrei
// Cell name: inversor
// View name: schematic
subckt inversor GND IN OUT VDD
    TP0 (OUT IN VDD VDD) pfet l=290.0n w=2u nf=1 m=1 par=1 ad=830.0f \
        as=830.0f pd=4.74u ps=4.74u nrd=0.134 nrs=0.134 gcon=1 rsx=50 \
        dtemp=0 gns=0
    TN0 (OUT IN GND GND) nfet l=290.0n w=2u nf=1 m=1 par=1 ad=830.0f \
        as=830.0f pd=4.74u ps=4.74u nrd=0.134 nrs=0.134 gcon=1 lstis=1 \
        sa=460.00n sb=460.00n sd=0 rsx=50 dtemp=0 gns=0
ends inversor
// End of subcircuit definition.

// Library name: patruzecisitrei
// Cell name: oscilator
// View name: schematic
I2 (0 net4 net3 vdd!) inversor
I1 (0 net04 net4 vdd!) inversor
I0 (0 net3 net5 vdd!) inversor
IPRB0 (net5 net04) iprobe
include "./_graphical_stimuli.scs"
ic net3=0 
simulatorOptions options reltol=100e-6 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 homotopy=all limit=delta scalem=1.0 scale=1.0 \
    compatible=spice2 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 digits=5 \
    cols=80 pivrel=1e-3 sensfile="../psf/sens.output" checklimitdest=psf \
    enable_pre_ver=yes ignorezerovar=yes 
pss  (  net3  0  )  pss  fund=1G  harms=10  errpreset=moderate
+    oscic=lin  annotate=status
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
saveOptions options save=allpub



pancho_hideboo said:
If you use Cadence Spectre and hidden states of 'nfet_ahdl' and 'pfet_ahdl' are not true but faik, add following in them.
Code: 
(* ignore_hidden_state *)
Click to expand...
Where do I add this? I can't find any command line in spectre...
 

catalin560 said:
Where do I add this?
Click to expand...
In Verilog-A modules.

Code: 
include "/work/tdk/AMS/H18/4.11/spectre/h18/soac/cmos53.scs" section=cmostm
I think some Verilog-A modules are called in "cmos53.scs".

catalin560 said:
I can't find any command line in spectre...
Click to expand...
Surely understand Simulator.
There is no option for Cadence Spectre.

In https://www.edaboard.com/showthread.php?t=368870#14, you did PSS/Pnoise Analysis.
However there is no Pnoise Statement in https://www.edaboard.com/showthread.php?t=368870#21.

There is an autonomous Shooting-Newton-PSS analysis statement only.
Code: 
pss  (  net3  0  )  pss  fund=1G  harms=10  errpreset=moderate
+    oscic=lin  annotate=status

And why did not you face hidden state problem in https://www.edaboard.com/showthread.php?t=368870#14 ?

You have to keep consistency through thread.
 
Last edited:

You may need to look into the simulation scheme, the
choice of models-set or the stop-views to ensure that
no veriloga or .ahdl "stuff" is included. A RF FET ought not
to point at such things but maybe you went and used
digital FETs which are invoking digital models by default.
 

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