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    How to avoid using clock trees in Zynq FPGAs?

    Dear all,

    I am designing some ring oscillators implemented in a Zynq 7000 FPGA and I have designed a period counter in order to measure the frequency of each ring oscillator. The clock signal of period counter is the output signal of the ring oscillator. My period counter is a synchronous counter that means all of its D flip-flops change state at the rising edge of the clock signal.

    My teacher said you HAVE TO come up with an Asynchronous period counter than a synchronous one since the number of clock trees in FPGA is limited and if you put for example 100 ring oscillators each individually connected to a period counter, you will see the problem of lack of the number of clock trees. First of all, is it correct??

    He also says, you have to force Vivado (I use 2017.1 version) NOT TO USE clock trees in your design and you have to change your period counter to an asynchronous one designed with T flip-flops. Is it possible to avoid using clock trees in design by a command or constraint in Vivado? Can you please let me know how?

    Also, my current period meter works very nice but I have no idea how to change it to an asynchronous by T flip-flops??!! Can anybody help me with those issues, please?

    kind replies and help are in advance appreciated.

    Regards,

    •   Alt15th June 2017, 00:35

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    Re: How to avoid using clock trees in Zynq FPGAs?

    Quote Originally Posted by msdarvishi View Post
    My teacher said you HAVE TO come up with an Asynchronous period counter than a synchronous one since the number of clock trees in FPGA is limited and if you put for example 100 ring oscillators each individually connected to a period counter, you will see the problem of lack of the number of clock trees. First of all, is it correct??
    there are only so many regional and global clocks in each clock region of the device (not going to look it up for you in the zynq documentation).

    Quote Originally Posted by msdarvishi View Post
    He also says, you have to force Vivado (I use 2017.1 version) NOT TO USE clock trees in your design and you have to change your period counter to an asynchronous one designed with T flip-flops. Is it possible to avoid using clock trees in design by a command or constraint in Vivado? Can you please let me know how?
    probably use the -bufg 0 in the synthesis options. Tells the tool there are no bufg's available.

    Quote Originally Posted by msdarvishi
    Also, my current period meter works very nice but I have no idea how to change it to an asynchronous by T flip-flops??!! Can anybody help me with those issues, please?
    pretty easy to find with a search...try that next time...https://www.cs.umd.edu/class/sum2003...eq/asynch.html



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    Re: How to avoid using clock trees in Zynq FPGAs?

    The FPGA has limited clocking resources. For example, a limit of 32 global clock buffers. It looks like the Zynq allows 12 BUFG and 4 BUFR connections per clock region. This limits the number of clocking resources to 32 + 4*Regions total clocks used.

    That said, you might be able to increase this limit by some amount. The FPGA also has BUFIO -- these can clock IO resources like the ISERDES. This clock is intended to be routed to a BUFR for use beyond the IO. If the ring oscialltors are slow in comparison to the system clock, you may be able to infer the number of cycles the ring oscillator has performed using the ISERDES module and a LUT to form a johnson counter. This could increase the total number by 4*Banks.



    •   Alt15th June 2017, 04:56

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    Re: How to avoid using clock trees in Zynq FPGAs?

    How is the use of a clock tree meaningful for this experiment? I am lost.
    Really, I am not Sam.



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    Re: How to avoid using clock trees in Zynq FPGAs?

    Quote Originally Posted by ThisIsNotSam View Post
    How is the use of a clock tree meaningful for this experiment? I am lost.
    Seems the OP is planning on having >100 ring oscillators in the Zynq and wants to put counters on all of them and is running out of clock domains (in the clock regions) in the FPGA.

    Sometimes I don't get what the point of some of these university "designs" are.



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    Re: How to avoid using clock trees in Zynq FPGAs?

    Quote Originally Posted by ads-ee View Post
    Seems the OP is planning on having >100 ring oscillators in the Zynq and wants to put counters on all of them and is running out of clock domains (in the clock regions) in the FPGA.

    Sometimes I don't get what the point of some of these university "designs" are.
    Dear @ads-ee,

    EXCELLENT !! You have conjectured correctly! That is my objective. Could you please help me out how to avoid using clock trees in this design??

    Thank you,

    - - - Updated - - -

    Quote Originally Posted by ads-ee View Post
    there are only so many regional and global clocks in each clock region of the device (not going to look it up for you in the zynq documentation).

    probably use the -bufg 0 in the synthesis options. Tells the tool there are no bufg's available.

    pretty easy to find with a search...try that next time...https://www.cs.umd.edu/class/sum2003...eq/asynch.html
    Dear ads-ee,

    Thanks for your reply. Based on your hint, I have looked at the clock distribution in Zynq FPGA and I see the clock trees originate from BUFGs. So, if I understood your point correctly, probably we have to put a constraint on BUFGs in XDC file not to activate them and not the synthesis tool to exploit them. Am I right?

    Thanks

    - - - Updated - - -

    Quote Originally Posted by vGoodtimes View Post
    The FPGA has limited clocking resources. For example, a limit of 32 global clock buffers. It looks like the Zynq allows 12 BUFG and 4 BUFR connections per clock region. This limits the number of clocking resources to 32 + 4*Regions total clocks used.

    That said, you might be able to increase this limit by some amount. The FPGA also has BUFIO -- these can clock IO resources like the ISERDES. This clock is intended to be routed to a BUFR for use beyond the IO. If the ring oscialltors are slow in comparison to the system clock, you may be able to infer the number of cycles the ring oscillator has performed using the ISERDES module and a LUT to form a johnson counter. This could increase the total number by 4*Banks.
    Dear @vGoodtimes,

    Thanks for your reply. Really , I did not understood your point and explanation ! Can you please explain me in more details? Also the formula that you have said : "32 + 4*Regions" isn't it 12 instead of 32as you described?

    Regards,



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    Re: How to avoid using clock trees in Zynq FPGAs?

    Quote Originally Posted by msdarvishi View Post
    Thanks for your reply. Based on your hint, I have looked at the clock distribution in Zynq FPGA and I see the clock trees originate from BUFGs. So, if I understood your point correctly, probably we have to put a constraint on BUFGs in XDC file not to activate them and not the synthesis tool to exploit them. Am I right?
    I already told you how to do this in post #2...
    -bufg 0 in the synthesis options. Tells the tool there are no bufg's available.
    This is done in synthesis it is NOT an XDC constraint.



    •   Alt6th July 2017, 00:35

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    Re: How to avoid using clock trees in Zynq FPGAs?

    My advice was based on the clocking guide. The FPGA is divided into a number of clock regions. Each region appears to have 12 BUFG nets and 4 BUFR nets. A more accurate version would be max(12*Regions, MaxBufgCount) + 4*Regions. The smallest devices could be limited to 12+4 or 24+8 BUFG+BUFR. Larger devices would have 32+4*Regions. I'm not certain if you can clock logic from fabric clocks without routing to a BUFG/BUFR. That is something you should determine first as that might allow more clocks. You are doing something that is not normally done in an FPGA. I'm not certain you can even source every clock buffer from independent fabric sources. I don't think I've ever needed more than one fabric-routed clock source in any design. Fabric-routed clocks are normally the result of a mistake during the design phase.



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