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  1. #1
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    A pseudo-random number generator

    Hi,
    I'd like to generate pseudo-random numbers in my synthesizable VHDL design. I've found this code : https://github.com/jorisvr/vhdl_prng...ro128plus.vhdl and it looks great but the seed is stuck to zero in the top-level component. I would like the seed to be different each time I run the design. Is there a way (maybe the time, the temperature,...) ?

    •   Alt13th June 2017, 10:25

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  2. #2
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    Re: A pseudo-random number generator

    You could make init_seed a port - connect it to a register map from a CPU and have the software set the seed and reset the design?



    •   Alt13th June 2017, 10:39

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  3. #3
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    Re: A pseudo-random number generator

    OK but the FPGA can not be separated from the CPU as a standalone component.



    •   Alt13th June 2017, 10:46

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  4. #4
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    Re: A pseudo-random number generator

    True randomness in an FPGA is very hard to configure and doesnt really exist.
    I have heard of people creating ring oscilators around the outside of the FPGA with large delays between luts so that combinations of the long routes and tempurature will give them some good randomness, but I have never seen it implemented.
    Hence why most people just use code similar to yours

    Why not just set the init_value to something non-zero when you instantiate the block?



  5. #5
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    Re: A pseudo-random number generator

    I'll see on the used board if something could be this non-zero value.
    Thank you.



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