Tarunfpga1
Newbie level 4
In my code there is a 80-bit register which is used and after synthesizing the code the no. of slices are 56, no. of LUTs are 224 and no. of Registers are 216. But in that code i replaced 80-bit register with BRAM (single port, synchronous, in write first mode) and after synthesizing this code the no. of slices are 90, LUTs are 229 and Registers are 136. So, it is understood that no. of registers will decrease so 216-80=136. But why no. of slices are increasing by 35 ? i have checked in the planhead tool and also in synthesis report that BRAM is not implementing in slices it is implementing in the alloted BRAM for fpga device.
i have used virtex 5 fpga.
Thanx!
i have used virtex 5 fpga.
Thanx!