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  1. #1
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    Synthesis: Check_Design Report too many warnings

    Hello everyone

    I have run DC. There were no error in my reports but there were a lot of warnings. I have attached some of the screenshots in my "check_design" report. Is this the reason why my formality test failed? If so, how can I reduced or eliminate the problem.

    •   Alt13th June 2017, 08:48

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  2. #2
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    Re: Synthesis: Check_Design Report too many warnings

    For one thing, it looks like you've got outputs connected to outputs. Not sure why that's only a warning and not an error. But I think you need to fix the problems that are causing the warnings if you don't want to see them...



    •   Alt13th June 2017, 17:38

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  3. #3
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    Re: Synthesis: Check_Design Report too many warnings

    barry I don't think the report is showing that outputs are shorted together.

    The report is saying you have an output port that is driven by a logic 1, i.e. the source of the output port is a logic 1.

    I also think there might be a connection problem on the alu_stat_wr[2] and alu_stat_wr[3] that needs to be looked at. Maybe the same statement is driving both ports.



    •   Alt13th June 2017, 18:56

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  4. #4
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    Re: Synthesis: Check_Design Report too many warnings

    is this ASIC or FPGA? looks like you forgot to add tiehi/tielo cells to the design.
    Really, I am not Sam.



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