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  1. #1
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    Synthesis: Check_Design Report too many warnings

    Hello everyone

    I have run DC. There were no error in my reports but there were a lot of warnings. I have attached some of the screenshots in my "check_design" report. Is this the reason why my formality test failed? If so, how can I reduced or eliminate the problem.

    •   Alt13th June 2017, 08:48

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  2. #2
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    Re: Synthesis: Check_Design Report too many warnings

    For one thing, it looks like you've got outputs connected to outputs. Not sure why that's only a warning and not an error. But I think you need to fix the problems that are causing the warnings if you don't want to see them...



    •   Alt13th June 2017, 17:38

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    Re: Synthesis: Check_Design Report too many warnings

    barry I don't think the report is showing that outputs are shorted together.

    The report is saying you have an output port that is driven by a logic 1, i.e. the source of the output port is a logic 1.

    I also think there might be a connection problem on the alu_stat_wr[2] and alu_stat_wr[3] that needs to be looked at. Maybe the same statement is driving both ports.



    •   Alt13th June 2017, 18:56

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    Re: Synthesis: Check_Design Report too many warnings

    is this ASIC or FPGA? looks like you forgot to add tiehi/tielo cells to the design.
    Really, I am not Sam.



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    Re: Synthesis: Check_Design Report too many warnings

    Also your debug probe, is it 1 bit size connected to a std_logic_vector? you may need to configure the tool



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    Re: Synthesis: Check_Design Report too many warnings

    Quote Originally Posted by wesleytaylor View Post
    Also your debug probe, is it 1 bit size connected to a std_logic_vector? you may need to configure the tool
    Im not sure where you see this - but this is not a problem. Often, 1 bit vectors come about when you have a component with a port sized by a generic (or it is generated code) and the size is set to 1.

    std_logic_vector(0 downto 0);



    •   Alt4th July 2017, 18:24

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    Re: Synthesis: Check_Design Report too many warnings

    #6 I'm aware of that

    What it looked like was
    deb_0 <= sig1
    deb_0 <= sig2

    Because all the signals are on the same net.

    Whereas, what I'd expect would be.
    deb_0(0) <= sig1
    deb_0(1) <= sig2

    Anyway. I believe I misread the error messages earlier so the point is moot.



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