CMOS cascode type amplifier design project

Hi,

So I've taken this fast track Analog course in which we have been assigned a design project. Besides the specs, we were also provided with 2 possible architectures referred from papers, and one of them is a folded cascode.

The problem is we hardly have any idea on how to really approach such design problems because firstly, we are new to analog design and secondly, this is a 1-month course which is usually 4 months. Having slides and such and understanding the smaller parts like the subcircuits isnt helping much because we have hardly gathered any experience/intuition in actually working out similar problems by ourselves.

The design consists of complementary diff input pairs (M1, M2 and M3, M4) with complementary current mirrors as active loads. They are in turn connected to a complementary cascode transistors (M7, M8). I have attached pictures of the circuit, specs, and some other related formulas.

I calculated the tail current from Cl and Slew rate (1000uA) but Im not sure as to how I would divide it across the branches. Following the paper I have fixed the ratio of the mirror M10:M9 and M5:M6 to be 1:1.2.

Do I extract the subcircuit components and work them out separately??


I am honestly in a terrible bind here, so IN CASE anyone is willing to help me even further by discussing intensively on how I should analyse the circuit to meet the specs, please feel free to inbox me, I'd be very obliged.

You didn't tell which CMOS technology is to be used, i.e. for which process you have (SPICE ?) simulation models. This would be rather important for the design.

The specified supply voltage VDD=3.3V indicates a 0.18µm process, whereas the original paper: F.Roewer and U.Kleine ”A Novel Class of Complementary Folded Cascode Opamps for Low Voltage” IEEE JSSC, August 2002, Vol. 37, No. 8, pp. 1080-1083 had been fabricated on a 0.8µm process. Can you get hold of this paper for good hints on your design?

erikl said:

You didn't tell which CMOS technology is to be used, i.e. for which process you have (SPICE ?) simulation models. This would be rather important for the design.

The specified supply voltage VDD=3.3V indicates a 0.18µm process, whereas the original paper: F.Roewer and U.Kleine ”A Novel Class of Complementary Folded Cascode Opamps for Low Voltage” IEEE JSSC, August 2002, Vol. 37, No. 8, pp. 1080-1083 had been fabricated on a 0.8µm process. Can you get hold of this paper for good hints on your design?

Click to expand...

I am ignoring the SPICE part of this for now and only sticking to hand calculations. Actually our design specs specify a 0.8um process as well as the paper but I am not sure whether that really matters for hand calculations (?). For now, all I have understood is that during slewing conditions, the output current should be equal to the tail current calculated from the slew rate which is 1000uA in this case.

I do have the paper but we were advised to only refer to the architecture there for our calculations because the paper doesnt describe the derivation of the gain formulas and such...

This exercise is asking you to learn its principles of operation in 1/4 the normal time. Start by simulating with simple circuits (M1, M2). Use an artificial (cheat) current source.
Later add the complex features.

When I simulate a basic differential amplifier I find there's a lot going on. It's essential to find a 'good operating point' so that you get sensible output as a result of changing either input voltage. Try applying(a) a fast square wave to one input, and (b) slow-frequency sine wave to the other input.

The output is a half-bridge, or combination of half-bridges. Its vital task is to create the correct output voltage, for any load resistance. There is a magic at work to produce this in the op amp, somewhere in the middle stage.

You seem to be tasked with optimizing a design but you
seem more focused on closed-form-solving it somehow.
I would not do that. Simulators (with proper models fitted)
are way more accurate than assumption-laden device
equations from textbooks based on long channel devices.

Depending on technology you may or may not be able
to meet all specs anyhow. Shunt compensation at the
output helps slew rate none. Be sure you understand
the required stability@loop gain and assume nothing -
slew rate vs gain-stable setting vs supply current is
one of the enduring "boxes" in op amp design.