+ Post New Thread
Results 1 to 9 of 9
  1. #1
    Member level 2
    Points: 257, Level: 3

    Join Date
    Feb 2017
    Posts
    49
    Helped
    0 / 0
    Points
    257
    Level
    3

    How to work out with "inout" port in verilog?

    Hi,
    I want to write into the memory through a port and sometimes after I have it read the memory content through the same port. How to do this? I am unfamiliar about inout port

  2. #2
    Advanced Member level 3
    Points: 6,250, Level: 18
    Achievements:
    7 years registered Created Blog entry
    dpaul's Avatar
    Join Date
    Jan 2008
    Location
    Germay
    Posts
    893
    Helped
    202 / 202
    Points
    6,250
    Level
    18
    Blog Entries
    1

    Re: How to work out with "inout" port in verilog?

    This post will be helpful.
    https://electronics.stackexchange.co...ort-in-verilog

    Learn how to use a tri-state buffer.
    Sharing my ideas and knowledge + learning from the experiences of others is what I am looking for.
    Spoon feeding is not my cup of coffee, so I am ready to show you the path, but it is you who has to walk through it!



    •   Alt13th June 2017, 08:27

      advertising

        
       

  3. #3
    Member level 2
    Points: 257, Level: 3

    Join Date
    Feb 2017
    Posts
    49
    Helped
    0 / 0
    Points
    257
    Level
    3

    Re: How to work out with "inout" port in verilog?

    Why people talk about i2c instantiation or tristate logic when it comes to inout port of verilog.



  4. #4
    Super Moderator
    Points: 230,196, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    39,747
    Helped
    12128 / 12128
    Points
    230,196
    Level
    100

    Re: How to work out with "inout" port in verilog?

    I2C uses inout to implement the open drain buffers. In standard I2C, the bus lines are either driven 0 or z, never 1.

    In hardware terms, a tri-state buffer is the equivalent of an inout. Bidirectional data busses, e.g. memory data lines need to use tri-state buffers at all connected ports.



    •   Alt13th June 2017, 11:05

      advertising

        
       

  5. #5
    Member level 2
    Points: 257, Level: 3

    Join Date
    Feb 2017
    Posts
    49
    Helped
    0 / 0
    Points
    257
    Level
    3

    Re: How to work out with "inout" port in verilog?

    Module design 1(
    Input clka,clkb,
    Input we,re,
    Input [3:0] addra,addrb,
    Input [3:0] data,
    Output reg [3:0]
    );
    Reg [3:0] ram [7:0];
    Reg [3:0] temp;
    always@(posedge clka)
    If(we)
    Ram[addra] <= data;

    always@(posedge clkb)
    If(re)
    Temp<= ram[addrb];
    Assign data = re ? Temp: 'dz;
    Endmodule
    This is both syntax free and synthesize able, but unable to write stimulus to "data" port. Tell me where it is wrong



  6. #6
    Advanced Member level 5
    Points: 33,436, Level: 44
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,127
    Helped
    1791 / 1791
    Points
    33,436
    Level
    44

    Re: How to work out with "inout" port in verilog?

    you need to declare "data" as inout, not input



  7. #7
    Member level 2
    Points: 257, Level: 3

    Join Date
    Feb 2017
    Posts
    49
    Helped
    0 / 0
    Points
    257
    Level
    3

    Re: How to work out with &quot;inout&quot; port in verilog?

    it is a typo mistake while typing in phone.

    - - - Updated - - -

    Quote Originally Posted by FvM View Post
    memory data lines need to use tri-state buffers at all connected ports.
    how should i use tri-state buffers in the code i posted here.
    Last edited by ads-ee; 13th June 2017 at 16:18. Reason: fixed tag



  8. #8
    Super Moderator
    Points: 230,196, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    39,747
    Helped
    12128 / 12128
    Points
    230,196
    Level
    100

    Re: How to work out with "inout" port in verilog?

    Your code already describes a 4-bit wide three-state buffer
    Code:
    data = re ? Temp: 'dz;



    •   Alt13th June 2017, 18:34

      advertising

        
       

  9. #9
    Super Moderator
    Points: 26,240, Level: 39
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    5,956
    Helped
    1462 / 1462
    Points
    26,240
    Level
    39

    Re: How to work out with &amp;quot;inout&amp;quot; port in verilog?

    Quote Originally Posted by hcu View Post
    it is a typo mistake while typing in phone.

    - - - Updated - - -

    how should i use tri-state buffers in the code i posted here.
    I'll assume that the mixed case keywords is also an artifact of using the phone.

    Code Verilog - [expand]
    1
    2
    3
    4
    
    Input [3:0] data,
    //has to be a typo too, because this won't compile?
    Output reg [3:0]
    );

    - - - Updated - - -

    This piece of code doesn't make a whole lot of sense:
    Code Verilog - [expand]
    1
    2
    3
    4
    
    always@(posedge clkb)
    If(re)
    Temp<= ram[addrb];
    Assign data = re ? Temp: 'dz;

    when a re pulses high for one clock cycle and is caught on the rising_edge of clock it will have gone away in the next cycle when the temp is assigned to data (in reality it will likely stick around for a few hundered ps due to Tco and routing delays). Only if re is high for two clock cycles with this work correctly, i.e. 1st clock reads the ram 2nd clock outputs the data. To properly enable the output you would have to use a delayed version of the re.



--[[ ]]--