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    Xilinx ISERDESE2 functionality with/without Bitslip

    Hi,

    I have been working on 7-series FPGA where I need to implement ISERDESE2 primitive. I am not getting any output out if it. Earlier I have implemented ISERDES2 on 6-series FPGA without bitslip operation. It was working. Now ISERDESE2 is not working. I understood Bitslip is for data alignment but how to implement the bitslip operation while using ISERDESE2 primitive. Please help me to resolve and understand the functionality of ISERDESE2 with and without Bitslip. I am posting my ISERDESE2 primitive here.

    Code Verilog - [expand]
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    ISERDESE2 #(
        .DATA_RATE      ("DDR"),           // DDR, SDR
        .DATA_WIDTH     (8),              // Parallel data width (2-8,10,14)
        .INTERFACE_TYPE("NETWORKING"),   // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
        .IOBDELAY       ("IFD"),           // NONE, BOTH, IBUF, IFD
        .NUM_CE         (1),                  // Number of clock enables (1,2)
        .SERDES_MODE    ("MASTER")      // MASTER, SLAVE 
    )
    ISERDESE2_inst (
        .O              (),  
        .Q1             (s_data_out[3]),
        .Q2             (s_data_out[2]),
        .Q3             (s_data_out[1]),
        .Q4             (s_data_out[0]),
        .Q5             (s_data_out[7]),
        .Q6             (s_data_out[6]),
        .Q7             (s_data_out[5]),
        .Q8             (s_data_out[4]),
        .SHIFTOUT1      (),
        .SHIFTOUT2      (),
        .BITSLIP            (1'b0),           
        .CE1                (1'b1),
        .CE2                (1'b1),
        .CLKDIVP            (1'b0), 
        .CLK                (rx_refclk),           
        .CLKB           (~rx_refclk),          
        .CLKDIV         (rx_refclk_div),       
        .OCLK           (1'b0),  
        .DYNCLKDIVSEL           (1'b0),
        .DYNCLKSEL      (1'b0), 
        .D              (1'b0),          
        .DDLY           (DATAOUT),       
        .OFB                (1'b0),          
        .OCLKB          (1'b0),          
        .RST                (i_sys_rst),
        .SHIFTIN1       (),
        .SHIFTIN2       () 
    );
    Thanks in advance.
    Last edited by FvM; 9th June 2017 at 11:25. Reason: Added syntax tags

    •   Alt9th June 2017, 11:23

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  2. #2
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    Re: Xilinx ISERDESE2 functionality with/without Bitslip

    I have never used the ISERDESE2 primitive, but it is a Xilinx IP and is well documented. Therein the Bitslip should be explained.

    Moreover
    I am not getting any output out if it.
    is a generic statement, you need to be specific about the problem and it would be good to be supported with some info (waveforms, etc).

    Earlier I have implemented ISERDES2 on 6-series FPGA without bitslip operation. It was working. Now ISERDESE2 is not working
    .
    That means you know something about the IP.
    But for series7, I guess you are using a later ver of Vivado. In many cases the Xilinx IPs get an upgrade. So you should check out the latest documentation and see what has changed.

    I am posting my ISERDESE2 primitive here.
    What you have posted is just the Verilog instantiation.
    .....yes, I do this for fun!



    •   Alt9th June 2017, 13:02

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  3. #3
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    Re: Xilinx ISERDESE2 functionality with/without Bitslip

    Code:
    .BITSLIP            (1'b0),
    You aren't implementing any bitslip that is why it doesn't work.

    Did you just hook it up like you did in 6-series (for a non-bitslip design)? Given the effort you've show with your question I suspect you just copied the 6-series code from somewhere and never read the documentation, so don't really know how to use it regardless of your claim of having implemented a working design. I think RTFM applies here, starting on page 143.



    •   Alt9th June 2017, 16:03

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    Re: Xilinx ISERDESE2 functionality with/without Bitslip

    @dpaul

    Thank you for your reply.

    I got where I did the mistake. I am doing OSERDES-ISERDES loopback. There should be a delay between the reset release and asserting OCE(output clock enable of OSERDESE2). The delay which I have given for OCE wasn't sufficient. So I increased the delay much more and OSERDESE2 started working. And so the ISERDESE2 also producing output. [Initially I had problem with OSERDESE2. so thought of testing ISERDESE2 alone first. Then I sorted out OSERDESE2 and ISERDESE2 also started working].

    But data mismatch is there in output side. Need to debug the same. Is it because of Bitslip? Is Bitslip mandatory to get proper data sequence from ISERDESE2? If so I need a clear idea of how to implement bitslip.

    Thanks.



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    Re: Xilinx ISERDESE2 functionality with/without Bitslip

    Bitslip is there to be able to align the data, which is why the protocols that use the ISERDES/OSERDES all have some sort of training sequence to determine the bit positions, so they know where MSB and LSB are in the serial data stream.



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