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how can I call a VHDL shared variables inside Verilog

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windtutelary

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hi all,

i have a problem with VHDL and verilog mixed ,

now VHDL and verilog is connect success,

VHDL is TOP and VHDL has a shared variables,

how can I call a VHDL shared variables inside Verilog code???

Thank you
 

by use $hdl_xmr can do it,
but shared variables array is VHDL declare a package,
and in verilog without instance can access it ??
 

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