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Variable width data pulse generator

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bit_an

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Hi

I wish to make a custom pulse pattern (see attachment). Typically the first bit should have larger duty cycle compare to the following bits. Also the following bits are random in nature...
I could write the code for making a random sequence. Could you please help me writing the addendum first bit?!

Thanks



data_input.JPG
 

What have you got so far and what problems are you having?
 

If the pulse width of the initial value is random in width then algorithmically you want to use the language's random function, i.e in Verilog $random, and perform the following operation:

random_width = $random % max_range_of_values + offset_starting value;

So if you want to have the number of bit times be 10-15...
random_width = $random % 6 + 10;

Of course none of this is synthesizable.
 

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