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  1. #1
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    vhdl 2008 external/hierarchy names assignments and alias

    I've read the following thread.

    http://www.edaboard.com/thread295879.html

    I can successfully assign something like the following (in concurrent part of architecture)
    Code VHDL - [expand]
    1
    
    APB_IN.PRDATA              <= << signal .SCP0466B1_tb.FPGA.PRDATA_S : std_logic_vector(31 downto 0)>>;

    however the following
    Code VHDL - [expand]
    1
    
    <<signal .SCP0466B1_tb.FPGA.PWDATA_S : std_logic >>                       <= APB_OUT.PWDATA
    just gives me a glitch see attached picture
    Click image for larger version. 

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    Also having problems with alias's
    Code VHDL - [expand]
    1
    2
    
    -- signal RDATA      : word32;
    alias PADDR_S is <<signal .SCP0466B1_tb.FPGA.PADDR_S  : std_logic_vector(31 downto 0) >>;
    modelsim gives
    ** Error: (vsim-8523) Cannot reference the signal "/scp0466b1_tb/FPGA/PADDR_S" before it has been elaborated.

    from verror -all log
    vsim Message # 8523:
    A signal must have been elaborated before it can be referenced in an

    external name.

    The default value for the type of the signal has been used.

    [DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names]

    [DOC: IEEE Std 1076-2008 VHDL LRM - 14.2 Elaboration of a design hierarchy]
    What am I doing wrong? Can't force concurrents apparently. Also does anyone have access to these sections of standard?
    Last edited by wesleytaylor; 8th June 2017 at 15:47.

    •   Alt8th June 2017, 15:34

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  2. #2
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    Re: vhdl 2008 external/hierarchy names assignments and alias

    Without seeing the code, I can only guess that this is a multiple driver error? Are all of the signals X rather than U after the glitch? it could be a delta issue with the driver result changing between deltas (because the direct assignment would occur 1 delta before a clocked assignment, for example).
    I would recommend NOT driving anything internally from a testbench via hierarchial references. It can be a little confusing, and anything like this really should be driven via the interface (although it does seem normal to use heirarchical drivers in SV simulation components - much to others confusion!)

    The elaboration problem will be because you are trying to access a signal in an entity that hasnt been instantiated yet. I guess you're trying to declare it in the declarative region of the architecture?
    All you need to do it move the alias declaration below the entity "FPGA" in the code - either locally in a process, or if you need it in several processes, wrap them up in a generate region:

    Code:
    FPGA : entity work.FPGA_ent port map ();
    
    multi_proc_gen : if true generate
      alias PADDR_S is <<signal .SCP0466B1_tb.FPGA.PADDR_S  : std_logic_vector(31 downto 0) >>;
    begin
      process ....
    
    
      process....
    
    end generate multi_proc_gen;



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