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What to do with unused input pins

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wtr

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Sure I haven't had issues before but microsemi is proving to be a nightmare.

imagine the following


Code VHDL - [expand]
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-- top level entity
CAMLINK_1_DATA              : in    std_logic_vector(27 downto 0);      -- MC13XX
--
 
-- somewhere in the code
    camera_A_data(0)  <= CAMLINK_1_DATA(0);
    camera_A_data(1)  <= CAMLINK_1_DATA(1);
    camera_A_data(2)  <= CAMLINK_1_DATA(2);
    camera_A_data(3)  <= CAMLINK_1_DATA(3);
    camera_A_data(4)  <= CAMLINK_1_DATA(4);
    camera_A_data(5)  <= CAMLINK_1_DATA(6);
    camera_A_data(6)  <= CAMLINK_1_DATA(27);
    camera_A_data(7)  <= CAMLINK_1_DATA(5);
    camera_A_data(8)  <= CAMLINK_1_DATA(7);
    camera_A_data(9)  <= CAMLINK_1_DATA(8);
    camera_A_data(10) <= CAMLINK_1_DATA(9);
    camera_A_data(11) <= CAMLINK_1_DATA(12);
    camera_A_data(12) <= CAMLINK_1_DATA(13);
    camera_A_data(13) <= CAMLINK_1_DATA(14);
    camera_A_data(14) <= CAMLINK_1_DATA(10);
    camera_A_data(15) <= CAMLINK_1_DATA(11);
    camera_A_fval     <= CAMLINK_1_DATA(25);
    camera_A_lval     <= CAMLINK_1_DATA(24);



Error message regarding the use of camlink_1_data(26, 19, etc, etc) basically they've been synthesised out.
What do I do. Compile crashes -the system

Regards
 

You haven't really shown what the error that Libero is producing during P&R or is this a Snyplify error?
 

I've got rid of them by

Concatenated the reject/rogue signals to make one register that then gets read into the cpu on the apb if an address (which is never used) is read. It hurts me to do this, just feels wrong, but it prevents synthesis purging the signal & thus I don't have to change my constraints or top level entity.

Ads-ee, unused IO get the following message
Warning: CMPG4-007: Top level port CAMLINK_1_DATA<15> is not connected to any IO pad.
 

Hi Tailor,
Have you interacted with Microsemi Technical Support team?
If not, please sent a mail to SoC_Tech@microsemi.com. One of the engineer will get in touch with you and will help you with a solution.

Thanks,
Rajesh Divipala.
 

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