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Ungrouping breaks ECO flow

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englishdogg

englishdogg

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In the example below my reference is to a functional ECO and not Timing ECO

By default synthesis performs ungroups as one of its basic optimization techniques to achieve better QoR.
Unfortunately this breaks my/users ECO flow

Lets say synthesis does ungroup and i have an ECO to do which i later do in my RTL and since my ECO is small (say 10 instances) usually i do manually since it is small.

How do i integrate that ECO when the design is ungrouped? difficult to identify hierarchies or to do this manually.
Lets also say i dont want to use any tool in the flow now (aware there are products in the market to achieve this - but will skip that for now)

Is there a way / flow/ methodology to this without re-synthesizing and re-doing teh whole flow again to achieve faster TaT.
 

englishdogg said:
In the example below my reference is to a functional ECO and not Timing ECO

By default synthesis performs ungroups as one of its basic optimization techniques to achieve better QoR.
Unfortunately this breaks my/users ECO flow

Lets say synthesis does ungroup and i have an ECO to do which i later do in my RTL and since my ECO is small (say 10 instances) usually i do manually since it is small.

How do i integrate that ECO when the design is ungrouped? difficult to identify hierarchies or to do this manually.
Lets also say i dont want to use any tool in the flow now (aware there are products in the market to achieve this - but will skip that for now)

Is there a way / flow/ methodology to this without re-synthesizing and re-doing teh whole flow again to achieve faster TaT.
Click to expand...

Use ungrouping at block level, but not at chip level.
 

Do you mean at SoC level which can be multi-million inst design?
Are you suggesting we do this flat synthesis later? how do i close my timing at the block level ?

Can you pls elaborate more in detail?
 

englishdogg said:
Do you mean at SoC level which can be multi-million inst design?
Are you suggesting we do this flat synthesis later? how do i close my timing at the block level ?

Can you pls elaborate more in detail?
Click to expand...

Ungrouping is not the default behavior. You have to specifically turn it on, at least for the tools I use.

Ungrouping is useful for enabling optimizations that go through hierarchical modules. It's impact on QoR really depends on the coding style, logic pruning, and retiming use. Maybe you should rethink the way you are doing it if ECO is a common task for your designs. I have done ungrouping for small modules/blocks, such that the hierarchy was *mostly* preserved at chip level, which has no ungrouping at all. At some point you will have to face the challenge of chip level ECO when everything is integrated. Without hierarchies, this is close to impossible.
 

To my knowledge all synthesis tools ungrouping is enabled by default. Be it Synopsys, Cadence or Mentor. Am almost certain on this one.

Like you mention not just opto across hier modules but logic decomposition and better structuring as well ungrouping helps- its not only about passing constants across hierarchies.

Rethink ECO ?? This is stable, concern is ungrouping when enabled ECO gets difficult. Its like a chicken and egg problem without ungrouping QoR is a concern with it ECO becomes difficult.
Understand this case - just that wanted to check if there is way to achieve it.

Also ECO is not something that is planned, but yes does occur sometimes.
 

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