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  1. #1
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    Fundamentals in Verilog

    Hi,

    I am new to verilog. Could you please explain what is the meaning of initial P = {(40-1){1'b0}};
    Next, what is the functionality of clock buffer and clock gate?!

    Thanks

    •   Alt6th June 2017, 18:05

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    Re: Fundamentals in Verilog

    Quote Originally Posted by bit_an View Post
    Hi,

    I am new to verilog. Could you please explain what is the meaning of initial P = {(40-1){1'b0}};
    Next, what is the functionality of clock buffer and clock gate?!

    Thanks
    initial is a procedure that is executed at time 0 and never executed again. In this case it assigns the 39-bit P a value of all 0's

    Clock buffer and clock gate don't have anything to do with Verilog.

    A clock buffer is exactly that a buffer for a clock, i.e. a clock driver that can handle the large amount of capacitive load on the clock tree. A clock gate is a gate in the path of the clock to enable disable the clock usually to reduce power consumption. Unless you use the dedicated clock mux in an FPGA (by instantiating it) it is really a bad idea to use gated clocks in an FPGA design and if you do instantiate this clock mux you better be sure you know how to write the timing constraints correctly..


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