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[moved] Slice count on FPGA ?

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Tarunfpga1

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There is a VHDL code which i synthesized for Xilinx Virtex-5 FPGA device. Now that is very small code which has 4-bit input and 4-bit output and it is purely combinational, no clk is used.
After synthesis i am getting the results which are as follows:
no. of LUTs - 4 which is understandable but no. of slices are used equal to 3.
Now, my question is that in virtex-5 a slice has 4 LUTs so if total 4 LUTs are utilizing then there should be only 1 slice but why it is showing 3 slices ??
 

no code, so can't see if there is something prohibiting the use of one slice.

Have you at least looked at the implemented results and how it partitioned the logic in a die view?

Most likely it was easier to place and route the 4 LUTs if not all placed in the same slice.
 

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