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[SOLVED] Extremely high leakage current in PMOS with AMS 0.35 um technology

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Wheatley

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Hi,

I am working with Cadence in an AMS 0.35 µm technology. I have a simple PMOS transistor layed out in a n-well over the general p-substrate. I am trying to measure the leakage current occurring because of the nwell-psub junction. For this purpose, I have tied to and the Source, Drain and Gate terminals and I am DC-sweeping the Body voltage from 0 V to 3.3 V. As I see it, I should see how the body current flowing from the Body terminal to the general substrate increases until reaching the reverse saturation current (around 0.3 fA, according to my calculations).

However, what I see is a huge leakage current increasing indefinitely at a constant rate of 2 fA/mV.

I attach a sketch for illustrating all of this.

NuevoDocumento 2017-06-06_1.jpg

Why is this happening?

Thanks in advanced!
 

To measure current between n-well and the p-substrate, you need to apply the voltage between the n-well tap (you do this) and substrate tap (you are not doing it, and you are not drawing substrate tap).
You can leave the terminals of the MOSFET floating.

What you are doing now is measuring the current through source/drain - n-well diodes. (why is source terminal not connected to drain/gate in your drawing, while you say that S/D/G terminal are shorted?).

2 fA/mV looks like a very high resistance (0.5e12 Ohm).

Max
 

First of all, thanks for your help Max!

Sorry, I should have sketched the substrate tap. The p-substrate is connected also to ground, so I am theoretically applying the voltage between well and substrate. At this point, I should mention that I am not 100% sure that the p-substrate connection to ground is well done in my layout, but I am more or less confident that it does is correct.

Besides, the source terminal is connected to/drain/gate/gnd in my drawing!

I can't figure why I am seeing a constant I/V rate if the nwell-psub forms a reverse-biased diode!

Thanks again.

David.
 

Your schematic is strange, that dashed line looks like you're trying to come up with a five terminal MOS symbol with both well and sub contacts, but you don't label them....

Can you show your setup in cadence?
 

Of course. I'll show three screenshots for illustrating the problem.

First, this is the layout of a PMOS transistor with its 4 terminals and 1 terminal (labeled as gnd) corresponding to the p-sub tap.

Captura de pantalla 2017-06-06 a las 18.52.33.png

Second, this is the testbench I am running.

Captura de pantalla 2017-06-06 a las 18.55.26.png

Third, this is the current flowing from the n-well tap to the p-sub tap (if I measure the current flowing into the "Vbulk" PIN and the current flowing from the "gnd" PIN, they coincide).

Captura de pantalla 2017-06-06 a las 18.55.40.png

Thanks for your help!

David.
 

The first question. What is gmin settings in your simulations? Are changing to other number affect the results, and does results following to gmin settings?
 
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    erikl

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The first question. What is gmin settings in your simulations? Are changing to other number affect the results, and does results following to gmin settings?

Wow, you think that Cadence is adding a transconductance of 2 pS between the n-well and the p-sub, right?

I don't have access to the Cadence machine until tomorrow, so I'll reply in 12 hours!

Thanks!
 

Not C@dence, most simulators - for DC and DC sweep simulations - add a transconductance gmin between the nodes of any semiconductor junction. The SPICE default value for gmin = 1e-12 , s. e.g. this PDF snippet:
 

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  • Solving_SPICE_Convergence_Problems_p3.pdf
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Second, this is the testbench I am running.

View attachment 139209
So you're biasing the nwell-psub junction, but also the nwell/S and nwell/D junctions. The nwell current (or bulk pin, in your case) will be a combination of these. So you're not just measuring the nwell-psub junction current there.
 

Not C@dence, most simulators - for DC and DC sweep simulations - add a transconductance gmin between the nodes of any semiconductor junction. The SPICE default value for gmin = 1e-12 , s. e.g. this PDF snippet:

Thats it! I've changed min to 1e-18 and everything is working as expected. The nwell-psub junction behaves as a reverse-biased diode.

So you're biasing the nwell-psub junction, but also the nwell/S and nwell/D junctions. The nwell current (or bulk pin, in your case) will be a combination of these. So you're not just measuring the nwell-psub junction current there.

I am measuring the current flowing into the nwell terminal and the current flowing from the psub terminal (they coincide). The other 3 terminals have no current.
 

So you're biasing the nwell-psub junction, but also the nwell/S and nwell/D junctions. The nwell current (or bulk pin, in your case) will be a combination of these. So you're not just measuring the nwell-psub junction current there.

I think the areas of the nwell/S and nwell/D junctions are neglectibly small compared to the nwell/psub junction, and so are their leakage currents.
 

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