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    Combinatorial loop and its effects ? how to avoid this ?

    Hi,

    my verilog code line at the end looks like this ,

    assign Total_result = x ? result1 : y ? result2 : Total_result ;

    This forms a combinatorial loop and linting tool shows error here and while vivado tool shows warning and tells timing may fail later.

    how can i rewrite this,
    if i use procedural assignment block like

    always@(posedge clk)

    Total_result = x ? result1 : y ? result2 : Total_result ;

    This may remove error, but the result will consume 1 clock cycle more which i dont want.
    some help is really appreciated.
    Last edited by FvM; 5th June 2017 at 07:39. Reason: Explicitely referring to FPGA tools, moved to FPGA section

    •   Alt5th June 2017, 06:25

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    Re: Combinatorial loop and its effects ? how to avoid this ?

    Hi,

    Neither in combinatorial, nor in clocked mode your formula will give useful results.
    What do you want to achieve with this?

    --> I assume you need an additional variable for the result.

    What initial value has Total_result? Maybe zero?
    Then the value will toggle with every clock cycle between 0 and infinite.

    Klaus



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    Re: Combinatorial loop and its effects ? how to avoid this ?

    It's legal Verilog code for a latch with input mux, I believe. You should know if a latch can work reliable in this place or if a clocked register is required. Prerequisite for correct latch operation is that all other inputs are stable when x or y are switching from transparent to latching state. Also x and y must have no glitches.

    Warnings should be expected in the former case, but which error do you see?

    Consider that asynchronous circuits are not well supported by FPGA timing synthesis tools.
    but the result will consume 1 clock cycle more which I don't want.
    In most cases, it's better to apply reasonable pipelining to a registered design than trying to fix a bad asynchronous construct.



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    Re: Combinatorial loop and its effects ? how to avoid this ?

    Do you need to assign it to itself if those conditions are not met?



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    Re: Combinatorial loop and its effects ? how to avoid this ?

    Quote Originally Posted by hcu View Post
    Hi,

    my verilog code line at the end looks like this ,

    assign Total_result = x ? result1 : y ? result2 : Total_result ;

    This forms a combinatorial loop and linting tool shows error here and while vivado tool shows warning and tells timing may fail later.

    how can i rewrite this,
    if i use procedural assignment block like

    always@(posedge clk)

    Total_result = x ? result1 : y ? result2 : Total_result ;

    This may remove error, but the result will consume 1 clock cycle more which i dont want.
    some help is really appreciated.
    This is naive code construction, latches should be avoided 99 out of 100 times. Make the block sequential like it should be. Pay attention to the difference between blocking and non-blocking assignments (= versus <=)
    Really, I am not Sam.



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    Re: Combinatorial loop and its effects ? how to avoid this ?

    Quote Originally Posted by wesleytaylor View Post
    Do you need to assign it to itself if those conditions are not met?
    no need! i have no thoughts , just to fullfill the syntax, i did that.

    - - - Updated - - -

    Quote Originally Posted by ThisIsNotSam View Post
    Pay attention to the difference between blocking and non-blocking assignments (= versus <=)
    I say it is a typo mistake. but anyhow for a single statement. it doesnot matter whether it is = or <=.

    - - - Updated - - -

    Quote Originally Posted by ThisIsNotSam View Post
    This is naive code construction, latches should be avoided 99 out of 100 times.
    see ! i have actually two srams in my design from where i read the data from those two memories periodically. As per status of some flags (here x andy )i should do multiplexing of those two data_out ports of memories.

    - - - Updated - - -



    •   Alt5th June 2017, 14:31

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  7. #7
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    Re: Combinatorial loop and its effects ? how to avoid this ?

    If you just want a mux, why did you implement a latch?

    Why not
    Code:
    assign Total_result = cond ? result1 : result2;



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    Re: Combinatorial loop and its effects ? how to avoid this ?

    Quote Originally Posted by hcu View Post
    no need! i have no thoughts , just to fullfill the syntax, i did that.

    - - - Updated - - -



    I say it is a typo mistake. but anyhow for a single statement. it doesnot matter whether it is = or <=.

    - - - Updated - - -



    see ! i have actually two srams in my design from where i read the data from those two memories periodically. As per status of some flags (here x andy )i should do multiplexing of those two data_out ports of memories.

    - - - Updated - - -
    It does matter. You will get simulation mismatches, lint errors, synthesis warnings, and most importantly will be mocked by your peers.

    I think you need a mux, like FvM said.
    Really, I am not Sam.



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    Re: Combinatorial loop and its effects ? how to avoid this ?

    If all hcu needs is a mux then they are writing their code with the thought process of a software coder.

    @hcu Look at all your code as hardware, if you want to select between two RAM outputs, think I need a multiplexer not think of some code like you initially proposed, where you treat a "variable" as some storage where you can read the value out of it and store it back into the same variable.
    Storage in software is easy to manipulate that way, storage written in that fashion in hardware ends up making latches. I see this all the time with interns writing code. Makes me wonder what the schools are teaching engineering students now days.



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    Re: Combinatorial loop and its effects ? how to avoid this ?

    Quote Originally Posted by FvM View Post
    If you just want a mux, why did you implement a latch?

    Why not
    Code:
    assign Total_result = cond ? result1 : result2;
    if my register x is high, i should select the data output of first ram.
    if my register y is high, i should select the data output of second ram.
    both x and y never gets high at the same time, forget about this.
    both x and y gets to low at the same time, where in this case, my port total_result shouldn't get data from either memories.
    how u do this?



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    Re: Combinatorial loop and its effects ? how to avoid this ?

    Use a combinational multiplexer...
    Code Verilog - [expand]
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    always @* begin
      case ({x,y})
        2'b10 : total_result <= result1;
        2'b01 : total_result <= result2;
        default : total_result <= 0;  // or whatever constant you want
      endcase
    end

    I also don't see the point in distinguishing that the output can't be either RAM when {x,y} == 2'b00 it shouldn't matter what the output is, as you probably shouldn't be looking at the total_result value when you have that condition.


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    •   Alt5th June 2017, 17:35

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    Re: Combinatorial loop and its effects ? how to avoid this ?

    Quote Originally Posted by ads-ee View Post
    Use a combinational multiplexer...
    Code Verilog - [expand]
    1
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    always @* begin
      case ({x,y})
        2'b10 : total_result <= result1;
        2'b01 : total_result <= result2;
        default : total_result <= 0;  // or whatever constant you want
      endcase
    end

    I also don't see the point in distinguishing that the output can't be either RAM when {x,y} == 2'b00 it shouldn't matter what the output is, as you probably shouldn't be looking at the total_result value when you have that condition.
    this removed combinatorial issue, but inferred latch . it is due to incomplete case statement.



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    Re: Combinatorial loop and its effects ? how to avoid this ?

    this removed combinatorial issue, but inferred latch . it is due to incomplete case statement.
    Unlikely. By adding the default case, it becomes complete. Guess your code is somehow different.



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    Re: Combinatorial loop and its effects ? how to avoid this ?

    To avoid timing, consider

    Code Verilog - [expand]
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    always@(posedge clk) begin
      Total_result_reg = Total_result;
    end
     
    //stuff
      Total_result = x ? result1 : y ? result2 : Total_result_reg ;



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