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24V reed switch interfacing with FPGA

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little0192

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Hello,

I am making a module to read the output from the magnetic reed switch working at 24V@20 mA using and FPGA.
For isolation i am using optoisolator 4N25. I am attaching the pics below for the configuration. Please let me know if there is something i can do to make this more robust.

I am confused about which configuration is the best out of the two. One gives me inverting output while the other is non-inverting. but thats not and issue.

Also, Let me know if there is a need for series resistance on the output signal line to control the sink current to the FPGA internal transistor.

P.S - i know i can use a resistor divider or a zener diode with a cap.

reed_1.PNG reed_2.PNG
 

I don't see a 4N25 base resistor suggested in any datasheet or application note. Where did you get it?

An FPGA pin configured as input doesn't source or sink current. In so far no current limiting is required.
 

Neither is "more robust". But a common emitter with light
pullup resistor (like 10Kohms) will get you to within Vce(sat)
of the ground rail, while a common collector with pulldown
resistor will drop ~ 0.7V (~0.8V @ low temp) from the V3p3
supply. This is likely to produce higher than expected I/O
supply current when "on".

Since the switch is slow and maybe bouncey, you probably
do not want a fast opto action. Let the saturation filter
out some of the chatter. Might want to "debounce in code"
inside the FPGA.

If the FPGA pin multipurpose I/O includes a pullup, pulldown
resistor option that might save you some pennies at the
board BOM level. I'd recommend a Schmitt input if that
is available to you (either by option or by default).
 

Hi,

Why do you use an optocoupler? The reed relay already is fully isolating.

Klaus
 

Maybe his reed switch and its 24V pullup are not as
close-in as the schematic makes it appear. A better
drawing indicating the harness / connectors would be
helpful.

Obviously if they were uncommitted reed contacts
near the board, then using them with a local pullup
to I/O voltage would eliminate some junk. But I expect
these are "plant features" to which a new FPGA based
whatzit is being interfaced, to.
 

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