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use a wr__rd_b select to decide which operation you are doing (can be a simple wr__rd_b <= ~wr__rd_b; toggle if you can tolerate it being free running). Verilog or VHDL has nothing to do with the problem, you need to design the circuit to do this function first. Translating it to Verilog (or VHDL) is the easy part.
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