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OpAmp Design for Voltage Reference

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Dragon65

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Good afternoon!
I need to design CMOS OpAmp on TSMC p/nmos 180nm for voltage reference.
Attached OpAmp: Opamp.PNG

Here i have a trouble - the right transistor of the bottom current mirror is not in saturation mode - the voltage drop on it is 300mV and the Gain i have -30dB - how can i improve my circuit?
Any advise, thanks)

Also is there some literature to improve my design skill in it?)
 

If you mean transistor X9, its Vds voltage is actually forced by the input common mode. In detail: in conventional operation the differential inputs would be close enough (real ground should be close to virtual ground even if the DC voltages are different) so two input transistors sink almost the same amount of current and they share a source node. The voltage at the source node should be equal to Input common mode level level (vinp + vinn / 2) minus whatever voltage is needed to turn the input transistors on. If you choose the common mode something higher the voltage drop on the current source will increase and if you choose it lower it will decrease. This is a fundamental problem that limits the input range of OPAMPs because there's no ideal current source.

What you can do is that you can reduce the vdssat voltage of the current mirror so that the unusable range is smaller (the region it goes out of saturation). You can do this by increasing the size of it, but how good it will be is debatable in a practical implementation. Also if the reported regions in the simulator includes the sub-threshold it may be in that region if the size of the transistor is too large for the amount of current flows through the biasing branch (which by the way may have very bad PSRR performance)

For the gain I need to look at this in more detail, I can't really comment on that. It may also be related to other biasing issues if it is significantly lower than what you were expecting, I'm just talking about the tail current source here.

An OPAMP book that I like a bit is Vadim Ivanov's book, I forgot its name though. It's extremely straightforward and mostly talks about conventional implementations of many blocks required in OPAMP design, it's a bit old but I like it. There are other books you can follow as well, but this one is the one came to my mind first.
 

A classical standalone op amp may not be what you
want. Many voltage references can be made much
simpler (what accuracy are you going for?) and it
might be acceptable to use a very simple op amp if
you just use it to push a cascode gate node above
the bandgap pair, with a cascode current mirror
above.

I'm not convinced that you need the tail sink to be
in saturation. Nor that it not being so, accounts for
your way-whacked gain number. Difference between
80dB and 70dB gain, maybe. -30dB, you've got a whole
'nother problem. Like maybe simulation or next-level-up
setup.

Your Ls look pretty short for something that wants high
single stage gain.
 

So now with this schematic i have 55 dB Gain - but it's small for my Voltage reference(I want Vref = 1.8 V). Can you give me some advise about design error amplifier - how improve gain and choose proper design?
Maybe for this purpose use MATLAB?
 

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