Reading and Writting to a RAM at the same time

Hi guys,
I'm doing a project and I came to a problem, maybe two.
I'm using a RAM that stores 18 : std_logic_vectors(6 downto 0). I'm using two counters in this project, one changes the adress and the other changes the value on that adress. Both values of the counters are being shown on the HEX of the board.
The problema is:
- When i change a value, on some of the adresses, it appears to change right (even two the numbers looked bugged on the HEX) but and when i change to a higher adress the value i put on other adress seems to follow and make those next adresses with the same or other value that i didn't put at start.

Code:

library ieee;
use ieee.std_logic_1164.all;

entity single_port_ram is
	port(
		Readclock	: in  std_logic;
		WriteClock  : in  std_logic;
		address	   : in  natural range 0 to 17;
		writeData	: in  std_logic_vector(6 downto 0);
		reset       : in  std_logic;
		load        : in  std_logic;
		
		
		currentData : out std_logic_vector(6 downto 0);
		readData1   : out std_logic_vector(6 downto 0);
		readData2   : out std_logic_vector(6 downto 0);
		readData3   : out std_logic_vector(6 downto 0);
		readData4   : out std_logic_vector(6 downto 0);
		readData5   : out std_logic_vector(6 downto 0);
		readData6   : out std_logic_vector(6 downto 0);
		readData7   : out std_logic_vector(6 downto 0);
		readData8   : out std_logic_vector(6 downto 0);
		readData9   : out std_logic_vector(6 downto 0);
		readData10  : out std_logic_vector(6 downto 0);
		readData11  : out std_logic_vector(6 downto 0);
		readData12  : out std_logic_vector(6 downto 0);
		readData13  : out std_logic_vector(6 downto 0);
		readData14  : out std_logic_vector(6 downto 0);
		readData15  : out std_logic_vector(6 downto 0);
		readData16  : out std_logic_vector(6 downto 0);
		readData17  : out std_logic_vector(6 downto 0)
	);

end single_port_ram;

architecture rtl of single_port_ram is
	subtype TWord      is std_logic_vector(6 downto 0);
	type    TMemory    is array(17 downto 0) of TWord;
	signal  s_memory : TMemory;
	signal  addr_reg : natural range 0 to 17;
begin

	process(WriteClock)
	begin
		if(rising_edge(clock)) then
			s_memory(address) <= writeData;
			if (reset = '1') then
				s_memory(1)  <= (others => '0');
				s_memory(2)  <= (others => '0');
				s_memory(3)  <= (others => '0');
				s_memory(4)  <= (others => '0');
				s_memory(5)  <= (others => '0');
				s_memory(6)  <= (others => '0');
				s_memory(7)  <= (others => '0');
				s_memory(8)  <= (others => '0');
				s_memory(9)  <= (others => '0');
				s_memory(10) <= (others => '0');
				s_memory(11) <= (others => '0');
				s_memory(12) <= (others => '0');
				s_memory(13) <= (others => '0');
				s_memory(14) <= (others => '0');
				s_memory(15) <= (others => '0');
				s_memory(16) <= (others => '0');
				s_memory(17) <= (others => '0');
			elsif (load = '1') then
				s_memory(1)  <= "1000000";
				s_memory(2)  <= "1000000";
				s_memory(3)  <= "1000000";
				s_memory(4)  <= "1000000";
				s_memory(5)  <= "1000000";
				s_memory(6)  <= "1000000";
				s_memory(7)  <= "1000000";
				s_memory(8)  <= "1000000";
				s_memory(9)  <= "1000000";
				s_memory(10) <= "1000000";
				s_memory(11) <= "1000000";
				s_memory(12) <= "1000000";
				s_memory(13) <= "1000000";
				s_memory(14) <= "1000000";
				s_memory(15) <= "1000000";
				s_memory(16) <= "1000000";
				s_memory(17) <= "1000000";
			end if;
		end if;
			addr_reg <= address;
	end process;
		
	process (ReadClock)
	begin
		if rising_edge(ReadClock) then
			readData1<= s_memory(1);
			readData2<= s_memory(2);
			readData3<= s_memory(3);
			readData4<= s_memory(4);
			readData5<= s_memory(5);
			readData6<= s_memory(6);
			readData7<= s_memory(7);
			readData8<= s_memory(8);
			readData9<= s_memory(9);
			readData10<= s_memory(10);
			readData11<= s_memory(11);
			readData12<= s_memory(12);
			readData13<= s_memory(13);
			readData14<= s_memory(14);
			readData15<= s_memory(15);
			readData16<= s_memory(16);
			readData17<= s_memory(17);
		end if;
	end process;
	
	currentData <= s_memory(addr_reg);
			
end rtl;

Click to expand...

In this project i need to be able to read the value that currently is stored on RAM and need to write to it at the same time. I'm not sure if the problem is on the RAM, i guess the problem is on the clocks i use (currently using 50MHz clock on the board), but i need some guidance . Any more code you need to look at just tell me.

I would not call that a RAM. It is some kind of register bank.

The problem you have is probably caused by the the line
being outside of the clocked part of the process. You should not have any code there.

std_match said:

I would not call that a RAM. It is some kind of register bank.

The problem you have is probably caused by the the line

Code:

			addr_reg <= address;

being outside of the clocked part of the process. You should not have any code there.

Click to expand...

I removed that signal completly and i'm now using the address input directly. Do you think that this "register bank" (and i admit it really is that) is fine? From my VWF it seems to work just fine but something with the clock should be wrong. In a hour i'll test it again and see if i'm successful.

The clock names don't match:


Try to use as few clocks as possible, and use strobes instead.
You don't want clock domain crossings where you easily can avoid them.

The design looks strange, but I don't understand what problem it is supposed to solve, so I can't say much about it.