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How do I add input delays when using external clocks in Actel FPGA. Because when I apply clock contstraints to external clock, negative slacks are produceds.
I am not sure I understand what you are trying to do.
Whenever you set an input delay constraint, it is set with respect to a clock. That means you are saying the external clock is in sync with the internal clock, witch I doubt is the case.
Basically I am receiving external seial data at 6MHz clock through a MicroD9 connector. Then I am writing this data coverting into bytes into FiFOs using the same clock as my write clock and a strobe signal associated with each byte as my Write enable. Reading is done at 12.5MHz.
This 60MHz clock is producing negative slack in my design. I read in the timing constraints note that we need to add input delays in case of negative slack. How much input delay is added for an external clock.what parameters should I consider? The timing constraints editor in designer is very confusing.
Basically I am receiving external seial data at 6MHz clock through a MicroD9 connector. Then I am writing this data coverting into bytes into FiFOs using the same clock as my write clock and a strobe signal associated with each byte as my Write enable. Reading is done at 12.5MHz.
This 60MHz clock is producing negative slack in my design. I read in the timing constraints note that we need to add input delays in case of negative slack. How much input delay is added for an external clock.what parameters should I consider? The timing constraints editor in designer is very confusing.
Can you please elaborate on what is wrong? I have defined the clock in sdc. On running synthesis, I am getting negative slack on this clock. Is there some other method of defining them?
You have another thread on this issue with negative slack.
Perhaps you should instead be providing us with the content of your constraint file that specifics the clocks for this interface along with the input constraints and the code for this interface you are having a problem with and perhaps a drawn timing diagram of what you expect the interface to see as the input data. Then we might understand what you are trying to accomplish, instead of providing incomprehensible symptom descriptions.
It isn't clear if the failing path is between two clock domains, entirely in one clock domain, involves only the IO interface, or includes logic in the FPGA.
Can you clarify that you have an external 6 MHz clock, you have a different 12.5 MHz clock, and "60 MHz" was a typo?
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