incisive29
Newbie level 6
How do I add input delays when using external clocks in Actel FPGA. Because when I apply clock contstraints to external clock, negative slacks are produceds.
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Basically I am receiving external seial data at 6MHz clock through a MicroD9 connector. Then I am writing this data coverting into bytes into FiFOs using the same clock as my write clock and a strobe signal associated with each byte as my Write enable. Reading is done at 12.5MHz.
This 60MHz clock is producing negative slack in my design. I read in the timing constraints note that we need to add input delays in case of negative slack. How much input delay is added for an external clock.what parameters should I consider? The timing constraints editor in designer is very confusing.