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[SOLVED] Crystal Oscillators instead of FPGA Clock

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Kibos

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Hello!

I am designing a TMR processor system. Each processor will get a clock input from a TMR clock. I finished the top level design of the system with the FPGA digital clock as reference to produce three outputs signals for each processor. I have provided synchronization through feedback, so synchronization is not a problem.
I was advised by an instructor to examine the possibility of using external crystall oscillators (hardware) and not the internal FPGA clock to prove fault masking manually by eliminating (ON/OFF) one clock at a time to manually demonstrate it.

I am using Altera DE10lite board for synthesis.

Now to the questions:
Can you use crystal oscillators to drive an FPGA processor design?
What are the risks of doing this?
Is it worth implementing it as an external module to add it (I/O pins) to the design, or just stick to the digital implementation?

Thanks!
 

I guess you are talking about triple modular redundancy processor system? I won't consider "tmr" a commonly understood technical term, so please don't use it without explaining it once in your post.

"Internal FPGA clock" is derived from a crystal oscillator as well. Using additional crystal clocks in your design is possible of course. You'll have to consider the effect of using asynchronous clock domains.

Is it worth implementing it as an external module to add it (I/O pins) to the design, or just stick to the digital implementation?
Not sure what you're asking here.
 

I think you are triplicating the clock distribution too? Otherwise I fail to see how an external clock would be more robust than an internal one.
 

Sorry for not explaining further. Triple modular redundancy is the term, correct. And I have triplicated the clock distribution, too let me explain more. The following design is what I have implemented internally in the FPGA. Each clock signal goes to a processor. The feedback is for the synchronization voting scheme.

clock_tick1.png
I was advised to examine the possibility of replacing the connection of the FPGA clock with crystals oscillators and connect it to I/O pins as a proof of concept for fault masking in the clock domain.

Is it possible to do this or should I stick to my current clock design?
If yes, How is it done? because I haven't used external oscillators to power an FPGA design before. One way I think is from A/D pins..
 

It is possible, sure, but are you certain this is sound? The clock source does not affect any failures due to SETs or physical defects. These will always happen at the clock tree, further down.

The image you posted is a combinational loop. Generally speaking, that is a terrible idea.
 
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    Kibos

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I kind of suspect that the circuit shown will likely never work in an FPGA, unless you hand place and route everything to do with that circuit. Even then it probably won't behave well at the opposite corners and you'll probably see a lot of skew between the three clocks and significant duty cycle distortion due to the feedback skew.

Sure it might simulate nicely as a behavioral description, but put in a bunch of random delays everywhere in the circuit (which is pretty much what you'll get from the implementation tools) to see what I mean.
 
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    Kibos

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So from the above mentioned information and some further research:
It is possible to use external oscillators but need complex handling when introduced as FPGA inputs, introduce a lot of problems in timing the signals correctly. Plus the extra hardware to implement it.
The proposed circuit when compiled with Quartus but had small amount of skew, correct.

Is there any advice on how to correctly implement the above task inside the FPGA? or it is not advised to do so using feedback?
 

I kind of suspect that the circuit shown will likely never work in an FPGA, unless you hand place and route everything to do with that circuit.

It might be my ignorance, but I don't even get the idea behind the logic network. In so far I'm unable to recognize if it "works" after the mentioned manual routing.
 

Thank you for your replies. Reading again all the posts I can understand that the advice I got is complex in the implementation and not advised to do so. I understand that:
It is possible to use external oscillators but need complex handling when introduced as FPGA inputs, introduce a lot of problems in timing the signals correctly. Plus the extra hardware to implement it.

Is there any advice on how to correctly implement the above task inside the FPGA? or it is not advised to do so using feedback?
 

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