Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Reading a block RAM Xilinx IP Core

Status
Not open for further replies.
B

beginner_EDA

Full Member level 4
Joined
Aug 14, 2013
Messages
191
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
3,854
Hi,
I have a video stream:
SAV :- Start of Active video
EAV :- End of Active video
Valid :- Valid video stream indicator
din(7 downto 0) :- Video Stream
Stream_Ready :- From component where stream is going.
I put a block RAM IP (xilinx) as buffer in between as follows:
Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

process (inter_clk,sys_rst)
begin
if sys_rst = '1' then
dina <= (others=>'0'); 
elsif rising_edge(inter_clk) then
if Stream_Ready= '1' and Valid = '1' then
Valid1 <= Valid;
SAV1 <= SAV;
EAV1 <= EAV;
dina <= din(7 downto 0); 
addra <= addra + 1;
else
Valid1 <= '0';
SAV <= '0';
EAV <= '0';
dina <= (others=>'0'); 
addra <= (others=>'0'); 
end if;
end if;
end process;
 
stream_ram_inst : stream_ram
PORT MAP (
clka => inter_clk,
ena => '1',
wea => Valid1,
addra => addra,
dina => dina,
douta => douta
);


and observe douta but nothing is coming out. Although all input I observe is correct.
How to read from RAM? Am i doing some mistakes here?
 

Code: 
stream_ram_inst : stream_ram
PORT MAP (
clka => inter_clk,
ena => '1',
wea => Valid1,
addra => addra,
dina => dina,
douta => douta
);

Whatever you have shown is logic to write-in data. I don't see any logic to read-out the data being written!

I also doubt the correctness of your instantiation of your 'stream_ram'. Recheck this.
 

The RAM will continuously read the content selected by addra and show it at douta port. You should be able to see it.

To read RAM content independent of write action, you'll probably want a dual port RAM with separate read address.
 

For a single port RAM, depending on the options used if you are using a read before write RAM the read operation will occur before the write so you won't see any of the data written until you cycle through all address of the RAM. If that is not the behavior you want then use a simple dual port RAM as FvM suggests.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top