oAwad
Full Member level 2
Hello all,
I want to introduce a special delay in clock signal for one gate in my layout design in SoC Encounter, is there a direct way to do it in SoC Encounter ?
* The design clock period is 2ns, while the delay that I want to introduce in the gate is 0.2ns
* The delay should be for this gate only not for the whole design.
if I increase the net length of the clock of that gate, can I achieve an 0.2ns delay ?
Thanks
I want to introduce a special delay in clock signal for one gate in my layout design in SoC Encounter, is there a direct way to do it in SoC Encounter ?
* The design clock period is 2ns, while the delay that I want to introduce in the gate is 0.2ns
* The delay should be for this gate only not for the whole design.
if I increase the net length of the clock of that gate, can I achieve an 0.2ns delay ?
Thanks