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PEX after dummy fill

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NovelPanda

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Dear All:

I am now running PEX after dummy fill and evaluate its impact. I use TSMC 40nm RF process with automatic dummy fill script provided by foundry. During the test of VCO, I use dummy blocker to enclose the varactor and interconnects, leaving other space automatically filled by dummy (the VCO core, subsequent buffer are all using RF NMOS with "RFDMY" layer enclosed), but KVCO did not change. The PEX is set to C+CC with gate level extraction, and all RF devices have been included in xcell. Post-layout simulation indicates that the VCO frequency drops 600MHz from 29GHz (post layout result without any dummy fill). The same frequency drops for all VCO bands. It seems that the dummy actually have large impact by adding parastics, and the layer "RFDMY" seems little help on reducing such a effect. I may want to know if I can enclose all sensitive RF NMOS by dummy blocker, and what will be the bad consequence if I inform the foundry to waive some density error if I have to. In addition, when I simulate the whole chip with dummy fill, the charge pump outputs zero current.

Thanks in advanced!
 

My understanding is that TSMC will not waive any density related violations. So that option is not really feasible. That being said, RF designs are fabbed all the time, and they are filled. You have to find a middle ground that works.
 

I recommend a "stimulus-response" approach where you
increase the dummy exclusion around specific features
(say, VCO core, Vtune line, buffer, ...) and see where the
difference in center frequency (or max, whatever) comes
in. Somewhere, between "none" and "as-is", a difference
between layouts will be found. Hopefully an area small
enough to not blow density rules, is all that needs fixed.

Even if it's "all of the above", with some midpoints at
some region-granularity you can at least arrive at an
engineering compromise.
 

Thanks! But what I found is that the dummy should be physically floating but "short" to ground during C+CC extraction? How come a 54um*54um Pad can have over 300fF capacitance with respect to the ground?
 

Dummies should indeed be floating (unless you tie them
explicitly, which could be a better idea than letting them
be a random sea of stray capacitance - which short-to-
ground fails to properly emulate).

A pad-stack with Met1 on the bottom might well have
that kind of shunt C, you'd have to check the field ox
thickness and do the calculation. Substrate is assumed
ground, I suppose, but you'd think shunt C would be to
psub! (maybe you use these interchangeably, maybe
the kit does (that would be bad for RF but not out of
the question for a digital-centric kit to insist that psub
is vss!). But you need to be clear in your own mind about
all that, I can only speculate.

A question is, where the fills' bottom connectivity gets
assigned (the to-ground capacitance). If there is a
"helper" symbol / spectre / schematic rep, maybe see if
you believe its contents or want to point to a more
reasonable, modified one (a simple enough matter for
root, if you can follow the chain to the cause).
 

This statement / question does not make sense to me:
But what I found is that the dummy should be physically floating but "short" to ground during C+CC extraction?
If your floating metal is not connected to any net (for example - lots of small metal squares/rectangles) - it is physically floating.
The first thing you should check is that your extraction tool is set up to treat floating metal as floating (as opposed to grounded).

In my experience, analog and RF designers usually avoid using automated fill utility for sensitive areas, and do manual fill, with either floating fill or with metals connected to some nets.

Regarding your high pad capacitance - is your pad connected to anything (metal routing, devices, etc.) that can have high capacitance to ground?

Max
 
Last edited by a moderator:

You might look at the fill cell construction. I have seen
some technologies where fills include active, contact and
alternating N+/P+ connected by Met1 -in which case, in
junction isolated CMOS of the regular sort, you -would-
then connect ohmically to the substrate.

Satisfy yourself regarding reality and then check the logic
of extraction.
 

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