How do I create an axi slave peripheral in vivado?

creating axi slave peripheral in vivado ?

Hello all,

I have a verilog design with a port list of

input clk_100Mhz,
input clk_50Mhz,
input rst,
input [7:0] DATA_P,
input control,
output [15:0] DATA_Q. I want to create axi slave peripheral. BTW I'm on Vivado.

I brought out a axi slave peripheral template in vivado with the options available. I instantiated my design just.
and now tell me how to port map my design signals with axi slave signals. I know very little about axi protocol.

Re: creating axi slave peripheral in vivado ?

hcu said:

I brought out a axi slave peripheral template in vivado with the options available. I instantiated my design just.
and now tell me how to port map my design signals with axi slave signals. I know very little about axi protocol.

Click to expand...

The AXI can't be directly connected to those signals you've got right now, what you have now is not a protocol it is just a bunch of random signals going into and out of some module. To interface with AXI you need to understand the AXI4 or AXI4-Lite protocol.

If you don't know the protocol then you should read the AXI specification or the Xilinx AXI document, before doing anything else. I'm not going to quote the entirre 328 page Amba AXI spec to you, or even the 175 pages of the Xilinx document.

Re: creating axi slave peripheral in vivado ?

thanks,
Today i learnt about axi lite , and the handshaking mechanism ,and all the 5 channels in it.
and even tried a 32 bit adder and verified on SDK. here what i have done is,

adder ports are :

input [31:0] a;
input [31:0] b;
output [31:0] sum;

here i connected the signal input a to a internal registers like slv_reg0; and b to slv-reg0 which are driven by s_axi_wdata. and later confused what to do with sum, i just connected to a vio block and verified the result on SDK and also in the vio core of vivado hardware manager.

I tried the same with my orignal design. but in SDK, xmd console. mrd and mwr are not working and saying "microblaze is ..... memory stall ..." something like that. BUt ddr 4 is ok .

Re: creating axi slave peripheral in vivado ?

To perform an AXI4-Lite read of sum the AXI master asesrts the AVALID and the ADDR (which you decode for reading the sum register) and looks for AREADY, once the master sees AVALID and AREADY both high it will wait for RVALID to be sent by the slave along with RDATA, once the master sees RVALID and it has captured the data it then it sets RREADY (the master can also set RREADY high immediately after the AVALID/AREADY if it can immediate accept the RVALID and RDATA). The slave then sees both RREADY and RVALID high ending the transfer by de-asserting RVALID and RDATA. Such transactions are described in the Xilinx AXI reference document.

As I recall there are some example designs on Xilinx's web site that use AXI4-Lite you could maybe look at those designs to get a feel for the logic used to interface to basic read/write registers.

Handshake for all transfers regardless of the channel are VALID and READY both active means the transfer is done and the side driving VALID de-asserts it. Either side can drive VALID or READY first. Neither side should wait for the other to do so.