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what if metastability settles to a wrong value

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twainerm

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Hi,
In a two flop synchronizer, what will happen if output of first flop settles to an in correct value due to metastabiltiy?
will it not be carried over to next flop as well and ultimately cause an error in the logic where synchronizer output is used?
Thank you for your time,
Mark
 

In applications using clock domain crossing, the bit being transmitted will tend to have some protocol that prevents there from being an invalid value.

For example, a pulse that stays high for several read-clock cycles.
 

By nature of metastability, there can't be a wrong value. Metastability occurs if a signal is sampled at it's edge, thus both levels are equally right. The problem of metastability is however, that the sampling register might not have settled to one level. The purpose of synchronizer is to decide for one level in this case and transfer it consistently to all data sinks.
 

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