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Need help with this code

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haneet

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Hi,
I'm trying a small piece of code and i'm not sure why my results are "x". Infact, the assigned value b in this code is also "x".

Code Verilog - [expand]
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module test;
 
wire a,b,c;
 
assign b=1'b1;
c=b;
 
initial begin
$display("output value c=%b b=%b",c,b);
end
assign #20 b=1'b0;
initial begin
$display("output value c=%b b=%b",c,b);
end
 
endmodule


Thanks in advance :)
 
Last edited by a moderator:

Yeah you can't assign it in two places at once, that is the same as shorting two wires on a board with a logic 1 and logic 0, the end result is the stronger driver wins. In simulation this results in an X for I'm unsure whether it is a 1 or 0.
 
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