haneet
Full Member level 3
Hi,
I'm trying a small piece of code and i'm not sure why my results are "x". Infact, the assigned value b in this code is also "x".
Thanks in advance
I'm trying a small piece of code and i'm not sure why my results are "x". Infact, the assigned value b in this code is also "x".
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module test; wire a,b,c; assign b=1'b1; c=b; initial begin $display("output value c=%b b=%b",c,b); end assign #20 b=1'b0; initial begin $display("output value c=%b b=%b",c,b); end endmodule
Thanks in advance
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