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transistor ageing in chip

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shweta.bphc

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Hi,

Can someone please explain what is transistor sizing and why does it happen?

Thank you!
 

Which is it - aging, or sizing?

its aging, like transistors degrade due to heating effects and all and slows down which results in slowing down the clock and performance degradation in chip. I want some more elaboration on reasoning part.
 

"Aging" is not really about time. Well designed parts with
attention to reliability can last a very long time without
drifting significantly.

But squeezing every last bit of speed out of a transistor
might lead you to push devices to (or past, with only a
"use model" for comfort) sensible stress limits. Many
"wearout" mechanisms are known (a semiconductor
reliability primer may be what you want). You have (for
MOS devices, the most ubiquitous and yet most fragile)
gate oxide wearout, hot carrier (HCI, NBTI), interconnect
wearout (electromigration) effects foremost. Gate ox
goes by applied field (which you maximize for drive) and
is exponentially accelerated by temperature. Interconnect
current stress goes up as your power-limited die continues
to trade lower voltage for higher current and yet decreases
metal pitch with every generation. Again acceleration by
stress and temperature. Working voltage for drawn L and
Tox is determined by the foundry based on reliability
expectations of the customers, and the more throw-away
the product is (perceived to be) the lower lifetime is
acceptable, guaranteeing (or to the cynic, actively
seeking) short wearout lifetimes.
 

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