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I got this "WARNING" during the step of generating bit file ? How to deal with

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hcu

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I got this "WARNING" during the step of generating bit file ? How to deal with

Hello all,

Firstly I am on ISE tool, Below is the part of my RTL. It showed me a warning like below and generated bit file successfully. how to deal with it, The statement itself shows it a bad design practice.
Code: 
wire read_ack8;
always@(posedge r_clk)
begin
	x18 <= x8;
	y18 <= y8;
end
assign read_ack8 = x18 | y18 ;

WARNING:PhysDesignRules:372 - Gated clock. Clock net read_ack8 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.

As the warning says, I dont have any CE pin in my port list.and also why read_ack8 is a clock net

where i am going wrong. can i code this in other way. but that idea may disturbs a huge part of the design.
 

Re: I got this &amp;quot;WARNING&amp;quot; during the step of generating bit file ? How to deal with

Are you using read_ack as a clock, i.e. using the read_ack in a posedge read_ack somewhere else in the design?

If that is the case then yes it is a bad design practice. After placement and routing there may be a difference in delay between x18 and y18 reaching the OR function which could result in possible glitches depending on the relationship between x18 and y18 outputs.

e.g.
Code: 
  ___     ___     ___  
_|   |___|   |___|   |_
   _______
__|       |____________  x18
            _______
___________|       |___  y18 skewed from x18
   _______  _______ 
__|       ||       |___  low going glitch due to skew

- - - Updated - - -

It would be better to use the following code to do exactly the same thing without a glitch.
Code Verilog - [expand]
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reg read_ack8;
always@(posedge r_clk)
begin
    read_ack8 <= x8 | y8;
end


Instead of ORing the tow outputs x18 and y18 or the inputs and then register it. If you need x18 and y18 then do both:
Code Verilog - [expand]
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reg read_ack8;
always@(posedge r_clk)
begin
    x18 <= x8;
    y18 <= y8;
    read_ack8 <= x8 | y8;
end


- - - Updated - - -

In general it is not a good idea to create logic generated clocks in an FPGA, but in this case I suspect you are using the read_ack8 as a clock to load a FF with a 1, which is then later cleared by a reset. Hopefully if this is the case you have properly synchronized the output of the FF to the other clock domain that is using the output.
 

Re: I got this &amp;quot;WARNING&amp;quot; during the step of generating bit file ? How to

Are you using read_ack as a clock, i.e. using the read_ack in a posedge read_ack somewhere else in the design?
Click to expand...

Iam very sure that read_ack is not a clock and never used in any always block sensitivity list.

i tried what u said, but this time got a new message like this:
WARNING:physDesignRules:372 - Gated clock. Clock net x18_y18_OR_50_o is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
Click to expand...
BTW "50_o" ? i dont know from where it come from.
 

Re: I got this "WARNING" during the step of generating bit file ? How to deal with

If you want help then you need to post all the code as the snippet is out of context as the problem exists somewhere else than in this specific piece of code.

Maybe either x18 or y18 are used as clocks somewhere else in the design. If clocks are being generated like this then I hope that the coders doing this are experienced engineers and know what they are doing. Or maybe x8 or y8 are used as clocks. If even one of the signals is used as a clock somewhere else you'll see problems like this propagated downstream where it is not used as a clock.

Is this ASIC emulation code? Most FPGA engineers don't add gated clocks because the tools complain about it and FPGAs are ill suited for doing that kind of design given there are no gated clock cells like there are in ASICs.
 

Re: I got this "WARNING" during the step of generating bit file ? How to deal with

Keep in mind that you can also infer latches that use read_ack8 as the clock for the latch. Check the design for latches. I forget what the warning is for this, but it shouldn't be too hard to find in the synthesis logs.
 

Re: I got this "WARNING" during the step of generating bit file ? How to deal with

Maybe either x18 or y18 are used as clocks somewhere else in the design
Click to expand...
I cant post all the code here and x18 y18 are not clocks.
 

Re: I got this "WARNING" during the step of generating bit file ? How to deal with

hcu said:
I cant post all the code here and x18 y18 are not clocks.
Click to expand...

Without the code - we can only go on the warnings supplied, which imply that they are being used as clocks elsewhere in the design.
 

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