hcu
Advanced Member level 4
I got this "WARNING" during the step of generating bit file ? How to deal with
Hello all,
Firstly I am on ISE tool, Below is the part of my RTL. It showed me a warning like below and generated bit file successfully. how to deal with it, The statement itself shows it a bad design practice.
As the warning says, I dont have any CE pin in my port list.and also why read_ack8 is a clock net
where i am going wrong. can i code this in other way. but that idea may disturbs a huge part of the design.
Hello all,
Firstly I am on ISE tool, Below is the part of my RTL. It showed me a warning like below and generated bit file successfully. how to deal with it, The statement itself shows it a bad design practice.
Code:
wire read_ack8;
always@(posedge r_clk)
begin
x18 <= x8;
y18 <= y8;
end
assign read_ack8 = x18 | y18 ;
WARNING:PhysDesignRules:372 - Gated clock. Clock net read_ack8 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
As the warning says, I dont have any CE pin in my port list.and also why read_ack8 is a clock net
where i am going wrong. can i code this in other way. but that idea may disturbs a huge part of the design.