Is this a good setup to test stability of linear LED current regulator?

Hello,
We wish to do stability testing on our linear LED current regulator. It is actually mains connected.
The designer tells us that he has some worry about instability occurring. He says that we should stick to a certain family of the Infineon range of FETs so that the circuit stays stable.
I must admit I have not had chance to do much stability testing with the hardware yet, but on the simulator, making even large changes to all the circuit values around this LED current regulator don’t appear to be bringing any instability at all.
Do you believe that the attached circuit diagram would be a valid test to check for instability of this current regulator?
The company will not mind me posting this bit of the circuit as its just a well known standard linear current regulator.
I also attach the LTspice simulation of the regulator.

Your sim looks good to inject and see the phase margin.
I don't think the MOSFET matters aside from parasitic capacitance. Op-amp U2 will correct for transconductance and dominant pole is set by C1/R12 470nsec 340kHz?

I would worry more about bridge rectifier reverse-recovery giving fast -ve spikes. Usually a tiny filter cap after the bridge even 1-10nF to snubber this as it can stress the LEDs. What is D96 B560C doing as a 60V part in a 339V string?

What is D96 B560C doing as a 60V part in a 339V string?

Click to expand...

Thanks, that diode never gets more than a few 100 millivolts volts across it in reverse.

I don't think the MOSFET matters aside from parasitic capacitance.

Click to expand...

Thanks, i tried putting in all kinds of capacitances gate to source, and it just refuses to go unstable....the stability of this circuit amazes me...i just cant seem to get it to go unstable unless using ridiculous circuit values around it.

I would worry more about bridge rectifier reverse-recovery giving fast -ve spikes.

Click to expand...

Thanks, I also considered that at first…..however, in our actual circuit, it is power factor corrected and there is no current flow during the zero crossings of the mains……the bridge diode voltages get gently taken down to zero volts…where current in them is zero, and then forward voltage grows gently in the next two bridge diodes, and due to this the reverse recovery spiking in these diodes is going to be extremely minimal. (because the current in them has fallen naturally to zero before they are then gently reverse biased)

Injecting a sine in transient analysis doesn't actually test or even measure phase margin. A pulsed current setpoint would be a better stability test.

The point of loop gain analysis is to visualize the actual phase margin and correct the compensation if necessary.
It would be done in an AC analysis with varying current set point parameter. The specific feature of this circuit is that output current modulates MOSFET gm and load impedance and thus varies the loop gain.

MOSFET gm, Cgs and Cds are in fact stability relevant. It seems however easy to give the circuit a large phase margin because it doesn't need to run in a speed competition.

Injecting a sine in transient analysis doesn't actually test or even measure phase margin.

Click to expand...

I know what you mean, it’s a “klunky” way of doing it.
As you know, we can get the phase margin at a particular frequency by injecting the voltage across the 50 ohm resistor, and then looking at the phase difference between the voltage waveforms at either side of the 50 ohm resistor..this gives us the phase margin at that frequency and set of conditions….admittedly this would be a slow way of getting phase margin over a large frequency sweep, so I know what you mean.

It looks like a fine way of simulating stability margins, assuming the actual circuit is built similarly. It's not surprising that the circuit is very stable, given that it's only a first order system. So long as the dominant pole in the closed loop transfer function is set by C1 and R12, you should be fine.