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Cadence SoC encounter IN LINUX

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DocIng

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how to use Cadence Soc Encounter

Hello,
I' want to use Cadence Soc Encounter to validate a prtotyping design.
I am very grateful if anyone can help me how can I use it. It seems me very difficult
 

Re: how to use Cadence Soc Encounter

Maybe start with a tutorial?
 

Hi
I want to use cadence SoC Encounter in linux centos6
I need a tutorial how to use it.
The command how to run it
 

DocIng said:
Hi
I want to use cadence SoC Encounter in linux centos6
I need a tutorial how to use it.
The command how to run it
Click to expand...

encounter runs smoothly on centos, maybe you don't know how to use it?
 

I run the cadence encounter. It is good;
Can you help me how prepare the data to import design in Encounter
How to prepare Gate level netlist (verilog)
SDC constraint and IO constraint?
 

DocIng said:
I run the cadence encounter. It is good;
Can you help me how prepare the data to import design in Encounter
How to prepare Gate level netlist (verilog)
SDC constraint and IO constraint?
Click to expand...

There are literally hundreds of tutorials on how to do these very basic tasks. If you struggle with some specific issue, I suggest you start a new thread.
 

For importing the different data for the design in SoC Encounter? need I instaling Synopsys design compiler ?
 

Can you help me,I am new in cadence encounter. Have you any idea how to obtain gate level netlist utilisant cadence
 

You are asking basically the same question in various forms again and again.

I repeat, STUDY the Cadence User Reference manual.
Ask your colleagues where to get it. How to obtain a netlist will be explained in the Cadence tutorial.

And yes, uploading copyrighted materials/docs is banned is here, so no one will provide you such tutorial here.
 

I want to using RTL compiler from cadence to obtain gate level netlist from verilog code.
I need the file synthesis.tcl ,I dont find it ; Should I build it?
 

I want to using RTL compiler from cadence to obtain gate level netlist from verilog code.
Click to expand...
Yes, feed your RTL design to Cadence RC with the options and if synth passes, you'll get the netlist.

I need the file synthesis.tcl ,I dont find it ; Should I build it?
Click to expand...
You team should already have one. Find it (ask your colleagues), modify it suitably and re-use it.
Else build your own.
How to build your TCL file? - Consult the Cadence RC user-guide tutorial. There will be a sample synth TCL script given there. Copy it, modify it and then run it in your environment.
 
Last edited:

Thanks you very much .I am the only one who works on the cadence tool, I am new in this field.
that I find a lot of problem.

- - - Updated - - -

I am the first who will work on the cadence tool,
I have no colleagues who can help me.
I am very grateful to help me
 

I am the first who will work on the cadence tool,
I have no colleagues who can help me.
Click to expand...

If you are unable to read and extract the necessary information from the Cadence documentation (in my opinion a normal engineer should be able to do that), then you should ask your company management to arrange a Cadence training session for you.
**broken link removed**
 

I am using the rtl compiler to synthesize a verilog code
the script of rtl compiler
Code: 
     set_attribute lib_search_path     my problem how I can choose the  path of library ?
     set_attribute hdl_search_path . 
     set_attribute library                       the target library?
     read_hdl -v2001 Counter.v 
     elaborate Counter
     set clock [define_clock -period 5000.0 -name clock clock] 
     external_delay -input {2500 2500 2500 2500} -clock clock  rstn 
     external_delay -input {2500 2500 2500 2500} -clock clock  updown 
     external_delay -output {2500 2500 2500 2500} -clock clock  count[*] 
     synthesize -to_mapped
     report area > area.rpt
     report timing > timing.rpt
     write_hdl -v2001 Counter > Counter.vh
 
Last edited by a moderator:

DocIng said:
I am using the rtl compiler to synthesize a verilog code
the script of rtl compiler
set_attribute lib_search_path my problem how I can choose the path of library ?
set_attribute hdl_search_path .
set_attribute library the target library?
read_hdl -v2001 Counter.v
elaborate Counter
set clock [define_clock -period 5000.0 -name clock clock]
external_delay -input {2500 2500 2500 2500} -clock clock rstn
external_delay -input {2500 2500 2500 2500} -clock clock updown
external_delay -output {2500 2500 2500 2500} -clock clock count[*]
synthesize -to_mapped
report area > area.rpt
report timing > timing.rpt
write_hdl -v2001 Counter > Counter.vh
Click to expand...

Ok, let me tell you this. Your question is so naive that it is absolutely impossible to say that you are prepared to synthesize any code at all. Go read tutorials, understand what synthesis is and what the inputs are.
 

I say that synthesis is a process from a software code lke verilog/Vhdl code to gate level netlist
The input are behaviroal RTL/description ,technology library,design environements,design constraints
The output optimised gate level netlist
 

DocIng said:
I say that synthesis is a process from a software code lke verilog/Vhdl code to gate level netlist
The input are behaviroal RTL/description ,technology library,design environements,design constraints
The output optimised gate level netlist
Click to expand...

I will be as polite as I can: you have no idea what you are doing if you have to come here and ask 'where the libraries are'.

Libraries are provided by the foundry or a 3rd party on their behalf -- but you only get them if your institution has signed an agreement with them.
 

I am using RTL compiler
Constraints a design
define_clock -period 100000 -fall 80 -rise 80 -name clkin /designs/TOP/ports_in/CLK
I have an error

Error : A required object parameter could not be found. [TUI-61] [path_group]
: An object of type 'instance|external_delay|clock|port|pin' named '' could not be found.
: Check to make sure that the object exists and is of the correct type. The 'what_is' command can be used to determine the type of an object.


ther TOP design is stored in /designs/TOP folder the level input ports are stored in/designs/TOP/ports_in
Can every body help me.Thanks
 

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