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    Working with a SPARTAN6 board

    There is a Xilinx Spartan6 board with a schematic file which shows how the pins are connected to the outside.
    Unfortunately, there is not enough information for some parts. According to the schematic and to reduce the IO
    pin counts, there is a 74595 (serial to parallel register) to access the LEDs and a 74165 (parallel to serial register) to read the push buttons.
    The schematic is not clear for me.
    I have written a simple 5-bit counter That when I push a button (SW4), the counter must count up by one unit.

    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    entity counter2 is
    	port( clk, rst: in std_logic;
    		  q: out integer range 0 to 31);
    end;
    architecture x of counter2 is
    begin
    	process( clk, rst )
    		variable tmp: integer := 0;
    	begin
    		if ( rst = '1' ) then
    			tmp := 0;
    		elsif (clk'event and clk = '1') then
    			tmp := tmp + 1;
    			if ( tmp = 32 ) then
    				tmp := 0;
    			end if;
    		end if;
    		q <= tmp;
    	end process;
    end;

    Problem is that I don't know how to assign the pins! For a Terasic Cyclone III board, it was easy to assign the pins.

    According to the schemtic, SW4->P4 of 74165. That means the input of the parallel to serial (PISO) is 00010000.
    In order to read that value, that register should be clocked five time to put the SW4 data on Q7 (DIP data). But what is that clock? The system clock has high speed. I have to use another button for clocking.

    Is that right? Please let me know how to read the input. Then I will discuss on how to put the counter's value on the output pins.

  2. #2
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    Re: Working with a SPARTAN6 board

    Hi,

    the schematic is OK and clear.

    You need to read both datasheets: 74165 and 74595.

    But what is that clock?
    --> it is marked as "CLK" in the schematic. = FPGA pin#32

    ***
    But I assume there are code examples for your FPGA board.

    Klaus



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    Re: Working with a SPARTAN6 board

    There is a PISO and SIPO sample code in the package. But, I don't know if I have to call them in my code or not.
    Although I have read the datasheets, still I don't understand how to read the push button!

    You said pin#32 is CLK. Is that the system clocks in the order of MHz? That will be fast!



    •   Alt18th May 2017, 14:06

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  4. #4
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    Re: Working with a SPARTAN6 board

    Hi,

    You said pin#32 is CLK.
    I know this by reading the schematic.

    The schematic also says it is a general purpose IO of the FPGA.

    Itīs not the system clock. Itīs just the clock signal for the two shift register ICs.
    The signal has to generated by code. --> sample code.

    ****
    Hint: Donīt hide the Spartan6 board name as a secret.
    There is a good chance that other forum members already used the same board and thus have experience with the LED/pus button interface.

    Klaus



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    Re: Working with a SPARTAN6 board

    It is an educational custom and the manual is non English. The board picture is here.

    The sample fodler for DIP and LED contains two VHDL files

    PISO
    Code:
    entity PISO is
    	generic (
    				g_DataWidth : integer := 16
    			);
    	Port ( 
    		i_CLK : in  STD_LOGIC;
    		i_Data : in  STD_LOGIC_VECTOR (g_DataWidth-1 downto 0);
    		o_CLK : out  STD_LOGIC;
    		o_Data : out  STD_LOGIC;
    		o_Latch : out  STD_LOGIC
    		  );
    end PISO;
    
    architecture Behavioral of PISO is
    
    signal s_Counter : integer range 0 to (g_DataWidth-1) := 0;
    signal s_Reg : STD_LOGIC_VECTOR (g_DataWidth-1 downto 0);
    
    begin
    o_CLK <= not i_CLK ;
    process(i_CLK)
    begin
    	if rising_edge(i_CLK) then
    		o_Latch <= '1';
    		if s_Counter = (g_DataWidth-1) then
    			o_Latch <= '0';
    			s_Reg <= i_Data;
    			o_Data <= s_Reg(0);
    			s_Counter <= 0;
    		else
    			o_Data <= s_Reg(0);
    			s_Reg(g_DataWidth-2 downto 0) <= s_Reg(g_DataWidth-1 downto 1);
    			s_Counter <= s_Counter + 1;
    		end if;
    		
    	end if;
    end process;
    end Behavioral;

    SIPO
    Code:
    entity SIPO is
    	generic (
    				g_DataWidth : integer := 16
    			);
    	Port ( 
    		i_CLK : in  STD_LOGIC;
    		o_Data : out  STD_LOGIC_VECTOR (g_DataWidth-1 downto 0);		
    		i_Data : in  STD_LOGIC;
    		o_CLK : out  STD_LOGIC;
    		o_Latch : out  STD_LOGIC
    		  );
    end SIPO;
    
    architecture Behavioral of SIPO is
    
    signal s_Counter : integer range 0 to (g_DataWidth-1) := 0;
    signal s_Reg : STD_LOGIC_VECTOR (g_DataWidth-1 downto 0);
    
    begin
    o_CLK <= not i_CLK ;
    process(i_CLK)
    begin
    	if rising_edge(i_CLK) then
    		o_Latch <= '1';
    		if s_Counter = (g_DataWidth-1) then
    			o_Latch <= '0';
    			o_Data <= s_Reg(g_DataWidth-2 downto 0)&i_Data;
    			s_Counter <= 0;
    		else
    			s_Reg(0) <= i_Data;
    			s_Reg(g_DataWidth-1 downto 1) <= s_Reg(g_DataWidth-2 downto 0);
    			s_Counter <= s_Counter + 1;
    		end if;
    		
    	end if;
    end process;
    end Behavioral;
    Thing that I don't understand is that what is the relation between SW4 which I want to use for counting up and the CLK pin of 74165? I want to push a button and see the LEDs count. That is all similar to the terasic cyclone.



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    Re: Working with a SPARTAN6 board

    Hi,

    slow down. go step by step.

    unfortunately there are two different "SW4" in the boardīs schematic.
    * one names a pushbutton (it generates a signal named "SW1")
    * the other names a signal (coming from pusbutton name "SW7")


    * pushbutton SW4 generates a signal "SW1"
    * signal "SW1" goes to 74165
    * there are other signals that go to 74165
    * now according 74165 datasheet you need to give CLK and PLoadn to the 74165 (you need FPGA code)
    * then the 74165 shifts out all input signals serially on DIPdata
    * inside the FPGA this serial datastream needs to be formed back into parallel signals (you need FPGA code)
    * now you have the signal of the pushbutton inside the FPGA available for your use (you say "count up")
    But you canīt use the SW4 pushutton to generate CLK for the 74165, because you FIRST need to use CLK to get the SW4 state into the FPGA.


    Klaus



    •   Alt18th May 2017, 18:13

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    Re: Working with a SPARTAN6 board

    The UCF file is

    Code:
    NET i_CLK			LOC = P127;
    
    NET o_LEDData		LOC = P29;
    NET o_PLoadn		LOC = P30;
    NET o_PSCLK			LOC = P32;
    NET i_DIPData		LOC = P33;
    NET o_Latch			LOC = P35;
    
    NET "*" IOSTANDARD = LVCMOS33;
    
    NET "i_CLK" TNM_NET = i_CLK;
    TIMESPEC TS_i_CLK = PERIOD "i_CLK" 50 MHz HIGH 50%;



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    Re: Working with a SPARTAN6 board

    * now according 74165 datasheet you need to give CLK and PLoadn to the 74165 (you need FPGA code)
    * then the 74165 shifts out all input signals serially on DIPdata
    Should I implement the CLK with another button? How many clock cycles does it take to send the pushed SW4 to the output of 74165?
    Also, which part of the sample code is needed?



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    Re: Working with a SPARTAN6 board

    Hi,

    Should I implement the CLK with another button?
    Again, more clearely: You canīt use any of the SWx inputs to generate CLK for the 74165, because you FIRST need to use CLK to get the SWx states into the FPGA.
    (And it usually makes no sense to use SWx to generate a clock signal. )

    How many clock cycles does it take to send the pushed SW4 to the output of 74165?
    Again: You need to read both datasheets: 74165 and 74595.
    And you need to clarify which "SW4" you mean.

    Also, which part of the sample code is needed?
    I didnīt go through the code...but:
    * SIPO seems to be: Serial In Parallel OUT....most probably useful for 74165
    * PISO seems to be: Parallel In Serial OUT....most probably useful for 74595

    Klaus



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    Re: Working with a SPARTAN6 board

    I understand what you are saying, but I don't understand how to implement the statements although I have read the datasheet multiple times.
    You canīt use any of the SWx inputs to generate CLK for the 74165
    Yes that is obvious since the CLK pin is not connected to any SW switches according to the schematic. I know that.

    because you FIRST need to use CLK to get the SWx states into the FPGA.
    This pin is driven by the FPGA (pin#32). But how? Which of the ports in my counter entity should drive that? I think you mean this pin is driven by the PISO code. So, does that mean I have to create a big entity which uses three components.
    1- the PISO component which gets the the SW pulse
    2- my counter which gets the output serial data (SW pulse) and feeds it to my clock signal used in the counter
    3- will be discussed later!

    I will appreciate if you guide me more.



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    Re: Working with a SPARTAN6 board

    Quote Originally Posted by mahmood.n View Post
    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    entity counter2 is
    	port( clk, rst: in std_logic;
    		  q: out integer range 0 to 31);
    end;
    architecture x of counter2 is
    begin
    	process( clk, rst )
    		variable tmp: integer := 0;
    	begin
    		if ( rst = '1' ) then
    			tmp := 0;
    		elsif (clk'event and clk = '1') then
    			tmp := tmp + 1;
    			if ( tmp = 32 ) then
    				tmp := 0;
    			end if;
    		end if;
    		q <= tmp;
    	end process;
    end;
    You use the signal clk in this code to run everything. If it is too fast to run those shift register parts then create a divider (i.e. a counter) and use the terminal count value to toggle another signal (the slow clock output) using clk. Keeps everything synchronous to clk (which is a good thing).

    In the above code get rid of the variable. As a new VHDL user using variables is a bad idea, it can get you into trouble with strange behavior and non-optimal code. Use a signal to generate your counter.



    •   Alt19th May 2017, 17:51

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    Re: Working with a SPARTAN6 board

    But note that according to the ucf file, NET o_PSCLK LOC = P32;. However, that signal is not used in the sample code. Does that mean I have to include that my code? I mean does CLK in my code is equal to o_PSCLK?



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    Re: Working with a SPARTAN6 board

    Quote Originally Posted by mahmood.n View Post
    But note that according to the ucf file, NET o_PSCLK LOC = P32;. However, that signal is not used in the sample code. Does that mean I have to include that my code? I mean does CLK in my code is equal to o_PSCLK?
    No you will use a clock input that has a free running oscillator attached to it. You will find that on a different bank of the FPGA. That clock will feed your entire design directly or through a DCM if you need a different frequency.

    I can see why you are struggling, you have a lack of understanding (or misunderstanding) of basic digital design concepts. This is compounded by the required use of an FPGA board, that has documentation that assumes you already know basic digital design concepts. Like flip-flops need a clock and that clock needs to be running all the time and that it has to be distributed on a global low skew net, etc, etc, etc,...

    Not sure what your background is, but you need to return to the basics first and learn them before tackling an FPGA design. Once you know the basics you apply that knowledge to designing in an FPGA. The approach right now seems more like, I don't know how to swim so I'm going to get dropped off 1 mile from shore and have to swim back to the beach.

    - - - Updated - - -

    BTW, from your UCF file it would be this pin:
    Code:
    NET i_CLK			LOC = P127;
    which is a 50 MHz clock input, probably from a 50 MHz oscillator.

    So your code should have a top level input port like i_CLK : in std_logic;

    You can see an example of this in the PISO and the SIPO code.



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    Re: Working with a SPARTAN6 board

    Well I have worked with terasic de0 and was able to run some simple designs. However, here I have confused with using switches to send data and the clock input



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