[SOLVED] verilog code for addition of contents in the memory

module opr(clock,di,dread,adr,in1,sum1,cmct);
input clock;
input [0:5] di;
reg [3:0] pn1;
input [3:0] in1;
output [0:5] dread;
input [1:0] adr;
 reg [3:0] k;
output [5:0]sum1;
reg [5:0]sum1;
output [3:0] cmct;
reg [3:0] cmct;
integer i,j;
 reg [0:5] ram1[0:3];
 reg en=1;
initial begin
 for (i=0; i<=3; i=i+1)
      begin
        ram1[i] <= 2'b00;   // memory initialization
      end				
end
assign  dread = ram1[adr];
   always @(posedge clock)
        begin
              if(en) begin        //storing   in memory
                 ram1[adr] <= di;
				 end
        end
initial  begin sum1=0; k=4'bzzzz; end
always @ (in1) begin
 sum1=0;
   for (i=0; i<=3; i=i+1)begin
	   for(j=0; j<6; j=j+1)begin      // calculating number of 1's
        sum1= sum1+ram1[i][j];
	
      end
  end
  
  if (sum1 >=6'b000110) begin
  pn1 = in1-4'b0001;
     cmct= pn1;
      k=pn1;	  end 
  else  cmct=k;	  //storing counter value in an array
  end 
  
endmodule