[SOLVED] Best practice for ommision of signals between synthesis and simulation

wtr · May 17, 2017

Hello all,

Take the following

Code VHDL - [expand]
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entity x is begin
  generic map (
  SIMULATION_G  : Boolean := false
  );
  port map(
    sig1  : in std_logic;
    sig12 : in std_logic;
    -- synthesis translate_off 
    sig13 : in std_logic;
    sig2  : out std_logic;
    -- synthesis translate_off 
    sig22 : out std_logic;
    sig23 : out std_logic
  );
end entity; --why the code entry font isn't monospaced is beyond me
 
 
architecture blah of x is 
 
begin 
---
G_SPOOF : if SIMULATION_G generate
  sig2  <= sig13;
end generate;

The above will always fail synthesis because the sig2 <= sig13 is witnessed & the signals for it are removed by the --synthesis translate_off. EVEN THOUGH I have a generic which tells the compiler to belay that order.

I don't know of a way to use the if - generate for an entity declaration. - would love to know peoples recommendation.

What recommendations do you have that could be used to generate a top level entity that is different for simulation compared to synthesis. It allows for signals to be routed out to the top so I can do bus functional models ...without having to simulate the cpu.

Regards,
Wes

- - - Updated - - -

I want something akin to the Verilog

Code Verilog - [expand]
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`define SIM
`ifdef SIM
the stuff i enter here exists in simulation code
`else
the stuff here is run the rest of the time
`endif

ThisIsNotSam · May 17, 2017

For this type of thing you can use a preprocessor, which would be very similar to what you get in verilog or in C.

See this: https://www.thecodingforums.com/threads/vhdl-has-no-define-like-verilog.24099/

FvM · May 17, 2017

I don't know of a way to use the if - generate for an entity declaration. - would love to know peoples recommendation.

You don't need to, simply define a default value for sig13 and omit the unused signals in the instantiation. You can even keep the logic related to sig2 and sig13, the synthesis tool will remove it if sig2 isn't connected in the instantiation.

ads-ee · May 17, 2017

Or use a newer version of VHDL (I think 2008, hopefully your simulation tool can handle it) and use the hierachical referencing that was "stolen" from Verilog. Then you don't need to add the ports you can access internal signals directly from your testbench.

TrickyDicky · May 17, 2017

ThisIsNotSam said:
For this type of thing you can use a preprocessor, which would be very similar to what you get in verilog or in C.

See this: https://www.thecodingforums.com/threads/vhdl-has-no-define-like-verilog.24099/

Not quite sure where this goes - as VHDL has no pre-processor.

I'd go with FvM's suggestion - give the inputs a default value and just leave them unconnected. using synthesis translate_on/off for ports seems just confusing to me really.

ThisIsNotSam · May 17, 2017

preprocessor is not exactly a language attribute, it's more of a tool support. you can use a C-like preprocessor on a VHDL code, this is what the link talks about.

vGoodtimes · May 18, 2017

This is reminding me of my preprocessor that added a for-python and other python-based features to VHDL and did a few other things.

The main issue with codegen is that you need some form of back-annotation for it to be practical. The tools need to know how to report that an error on line 500 of the derived file is actually an error on line 200 of the base file.

So my fancy python preprocessor wasn't really useful in the end. Every time I needed to use it, I managed to find an alternative. Usually by abusing report, generics, and functions that generate constants.

wtr · May 19, 2017

ThisIsNotSam said:
For this type of thing you can use a preprocessor, which would be very similar to what you get in verilog or in C.

See this: https://www.thecodingforums.com/threads/vhdl-has-no-define-like-verilog.24099/

I must admit this looks pretty powerful, however I'm stuck in a situation, where the computer system at work are locked down like a nun in chastity. They think it makes this place secure. In addition #7 makes a very good point.

Picking up

ads-ee said:
Or use a newer version of VHDL (I think 2008, hopefully your simulation tool can handle it) and use the hierachical referencing that was "stolen" from Verilog. Then you don't need to add the ports you can access internal signals directly from your testbench.

This is quite a nice alternative. Which doesn't require a code gen tool

I don't quite follow #3.
Please give example. My code is

Code VHDL - [expand]
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----toplevel entity
    -- synthesis translate_off                                        
    DEBUG_ARM_IN                : in    std_logic_vector(69 downto 0);      -- Debug ARM APB Bus Input      
    DEBUG_ARM_OUT               : out   std_logic_vector(33 downto 0);      -- Debug ARM APB Bus Output
    
    DEBUG_AXI_IN                : in    AXI_SLAVE_IN;                       -- Debug FDDR AXI Bus Input
    DEBUG_AXI_OUT               : out   AXI_SLAVE_OUT;                      -- Debug FDDR AXI Bus Input
    -- synthesis translate_on
-----------------------
----somewhere in toplevel
G_CPU_SPOOF: if SIMULATION_G generate
-- synthesis translate_off
  PWDATA_S                    <= DEBUG_ARM_IN(31 downto 0);
  PADDR_S                     <= DEBUG_ARM_IN(63 downto 32);
  PWRITE_S                    <= DEBUG_ARM_IN(64);
  PENABLE_S                   <= DEBUG_ARM_IN(65);
  PSEL_S                      <= DEBUG_ARM_IN(66);
  MSS_READY_S                 <= DEBUG_ARM_IN(67);
  
  CLK                         <= DEBUG_ARM_IN(68);
  CLKX3                       <= DEBUG_ARM_IN(69);
  
  DEBUG_ARM_OUT(31 downto 0)  <= PRDATA_S;
  DEBUG_ARM_OUT(32)           <= PREADY_S;
  DEBUG_ARM_OUT(33)           <= PAYLOAD_START_S(4);
-- synthesis translate_on
end generate;

THIS entity is the top and therefore the tool surely requires pin constraints! I think that's what force me to put -- synthesis translate_on/off tags round the code

TrickyDicky · May 19, 2017

wesleytaylor said:
I don't quite follow #3.
Please give example. My code is

Code VHDL - [expand]
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DEBUG_ARM_IN                : in    std_logic_vector(69 downto 0) := (others => '0');      -- Debug ARM APB Bus Input      
    DEBUG_ARM_OUT               : out   std_logic_vector(33 downto 0);      -- Debug ARM APB Bus Output
    
    DEBUG_AXI_IN                : in    AXI_SLAVE_IN := AXI_SLAVE_IN_DEFAULT;                       -- Debug FDDR AXI Bus Input
    DEBUG_AXI_OUT               : out   AXI_SLAVE_OUT;                      -- Debug FDDR AXI Bus Input

Here, the inputs can be left out of the port map as they have a default assignment they will be set to if left unconnected.

But if it really is debug ONLY for simulation - then use 2008 hierarchical referencing.

wtr · May 19, 2017

TrickyDicky said:

Code VHDL - [expand]
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DEBUG_ARM_IN                : in    std_logic_vector(69 downto 0) := (others => '0');      -- Debug ARM APB Bus Input      
    DEBUG_ARM_OUT               : out   std_logic_vector(33 downto 0);      -- Debug ARM APB Bus Output
    
    DEBUG_AXI_IN                : in    AXI_SLAVE_IN := AXI_SLAVE_IN_DEFAULT;                       -- Debug FDDR AXI Bus Input
    DEBUG_AXI_OUT               : out   AXI_SLAVE_OUT;                      -- Debug FDDR AXI Bus Input

Here, the inputs can be left out of the port map as they have a default assignment they will be set to if left unconnected.

But if it really is debug ONLY for simulation - then use 2008 hierarchical referencing.

When I do something like that the eda tools want pin association for the ports.

K-J · May 22, 2017

wesleytaylor said:
What recommendations do you have that could be used to generate a top level entity that is different for simulation compared to synthesis.

My recommendation is to not make a top level that is different between synthesis and simulation. Without an accurate simulation model of reality, then debug of real world problems can only be done on hardware which is not efficient.

It allows for signals to be routed out to the top so I can do bus functional models ...without having to simulate the cpu.

What is the problem with creating a simulation model for a CPU? You don't have to create the full model that fetches instructions from memory, decode, execute, repeat. Rather, you simply need to emulate the I/O bus and then write the code that emulates what the code in the real device will do for your application. Very simple.

Kevin Jennings

wtr · May 23, 2017

See #4 for solution

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[SOLVED] Best practice for ommision of signals between synthesis and simulation

wtr

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ThisIsNotSam

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FvM

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wtr

TrickyDicky

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ThisIsNotSam

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vGoodtimes

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FvM

wtr

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wtr

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K-J

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wtr

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