wtr
Full Member level 5
Hello all,
Take the following
The above will always fail synthesis because the sig2 <= sig13 is witnessed & the signals for it are removed by the --synthesis translate_off. EVEN THOUGH I have a generic which tells the compiler to belay that order.
I don't know of a way to use the if - generate for an entity declaration. - would love to know peoples recommendation.
What recommendations do you have that could be used to generate a top level entity that is different for simulation compared to synthesis. It allows for signals to be routed out to the top so I can do bus functional models ...without having to simulate the cpu.
Regards,
Wes
- - - Updated - - -
I want something akin to the Verilog
Take the following
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 entity x is begin generic map ( SIMULATION_G : Boolean := false ); port map( sig1 : in std_logic; sig12 : in std_logic; -- synthesis translate_off sig13 : in std_logic; sig2 : out std_logic; -- synthesis translate_off sig22 : out std_logic; sig23 : out std_logic ); end entity; --why the code entry font isn't monospaced is beyond me architecture blah of x is begin --- G_SPOOF : if SIMULATION_G generate sig2 <= sig13; end generate;
The above will always fail synthesis because the sig2 <= sig13 is witnessed & the signals for it are removed by the --synthesis translate_off. EVEN THOUGH I have a generic which tells the compiler to belay that order.
I don't know of a way to use the if - generate for an entity declaration. - would love to know peoples recommendation.
What recommendations do you have that could be used to generate a top level entity that is different for simulation compared to synthesis. It allows for signals to be routed out to the top so I can do bus functional models ...without having to simulate the cpu.
Regards,
Wes
- - - Updated - - -
I want something akin to the Verilog
Code Verilog - [expand] 1 2 3 4 5 6 `define SIM `ifdef SIM the stuff i enter here exists in simulation code `else the stuff here is run the rest of the time `endif