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[Moved:] PNP in CMOS different sizes

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CAMALEAO

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Hi everyone,

What's the difference between the different types of pnp bjts options in the process? Say for example between a pnp 5x5 and 10x10?

Regards.
 

Re: PNP in CMOS different sizes

The differences are obviously emitter area and periphery.
Area goes to the current density where peak hFE is found.
For low power you generally want smaller, to get best OP
hFE.

But small devices also have a larger periphery to area ratio
and some hFE degradation relates more to periphery than
areal current density - current injected laterally crosses a
wider (lower or no gain) base, tends to be recombined at
a substantial loss.

Larger features tend to match better / more consistently.
Meaning perhaps less scatter in your untrimmed bandgap
voltage & tempco.

You could see what the models show when put into classic
characterization testbenches (hFE vs Ic, w/ Vce - although
often the PNP is a diode connected substrate PNP used only
for bandgaps, in which case Vce=Vbe and you can cut down
on that dimension; Gummel plot, which can show you some
stuff about where and where is not, the log-Ic vs Vbe linear.

Then you would like to repeat this on a probe station or on
packaged units (perhaps arrays, since one is tiny) and see
just how much your foundry cared about accuracy on a
"freebie" (zero effort -> low expectations) transistor.
 

Hi dick,

I get you. However what is the main differences between them when using for a bandgap circuit? Is there any difference when it comes down to its usage on a bandgap?

Regards.
 

You have to look at the real emitter I-V curve (assume
B=C=substrate) and the modeled I-V curve and see
how these look about the intended operating point. A
BJT's Gummel plot (which you can't get perhaps, as
configured) has a region of log-linearity (where you
want to be) bounded above and below by some nonideal
behaviors. Too low a current and you start to deviate
due to nonideal base currents, this sets your minimum
useful emitter current density for precision references
and area, the useful minimum emitter current. Note that
you will see this range move with processing and temp,
so stay a decade or more up out of it.

As a rule low power favors smaller size, but again you
do not yet know whether smaller really means more
bothered by periphery effects. If this is to be a real
product, then you need to get real (on the bench).
If it's all just simulations, then use what you see there.
 

When you say then you need to get real, you mean like get real and use 10x10 or do the design with 2x2 and test/measure it on the bench?

I read about somewhere that I standard curve that normal people look at is the vbe vs current density. Do you have any idea where can I find a typical curve like this one? Or maybe even better how to simulate it?
 

I mean that this device is critical to reference accuracy
(especially if you mean to go untrimmed) and models lie.
Modeling group will stop at a "good enough" fit. But that's
good enough according to them, not the guy who's going
to be responsible for outcomes. Measure it. Measure it at
multiple decades of forced current with good Kelvin sense
at (say) 25C intervals from min to max application temp.
It has been the case with technologies I've used, that
diode temperature behavior cannot be fitted to adequate
accuracy using the tc params of the standard model,
and to do better you may have to fit a veriloga of your
own.

And do it for both geometries so you can see whether
your behavior vs current density shows true, and only,
current/area or whether there are unexplained
deviations - and which, in the end, the models you have
do the best job of emulating about the point where you
intend to operate.
 

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