Soi cmos partially depleted and floating body difference

Can any one tell the difference between floating body SOI CMOS and partially depleted CMOS?. Which configuration is preferred for RFIC Applications?

There is more to the distinction than that.

Fully depleted SOI means that at Vgs=0 the gate depletion
region extends to the back (oxide, sapphire) interface.
And more importantly to RF, enhancement builds a channel
that has less depth and more carriers as a result, for a
superior MOSFET behavior. In addition, since it's that
shallow a structure, S/D junctions are bottomed against
the insulator so there is zero bottom plate, and 1/4 the
sidewall Cdb, Csb - eliminating these capacitances as
loads / losses, and eliminating their nonlinear C-V as a
distortion / AC nonlinearity contributor.

Now, there remains a body pocket" below the gate, if
"fully depleted" at Vgs=0 this may be depleted of carriers.
But once the inversion sheet forms, the body below it
is now "floating". Body ties are either none, or ineffective
(highly resistive, gate modulated) making things like low
power continuous time analog design a real minefield -
kink effects in subthreshold / near-threshold operation,
RTN from the tiny body "popping" up or down by tens
of mV due to one detrapped carrier, etc.). This can get
short or no attention from RF technologists and designers
who are all about the high frequency, high current density
operation. Until they want a low power bias network or
something, and see "memory effects" and random sub-Hz
bias-point jumps, anf the finger points at you as the guy
who designed the block based on models that ignored the
details because nobody cared to look. So look, and look
again.

Another little icky-poo is that, with S/D touching the back
interface, you have a free MOSFET - lucky you. Its "gate"
is the handle (SOI) or just really thick sapphire (or sapphire
plus SiO2, worse yet for charge trapping). In cases where
the insulator is well thicker than the device film (usually the
case, for FD) fringing field from the drain can "wake up" the
back interface - this is one cause of "drain kink" (impact
ionization in the body pocket, and waking up the vestigial
BJT, is another). All of this would like a body tie, but too bad.

Partially depleted (PDSOI) means the gate has no authority
that extends to the back of the device. Basically it's like JI, in
a glass tub. Only every body is free and is up to you to connect
and control. You can float the body, tie it to source, tie it to
ground (ala psub! but explicitly), tie it to gate (dynamic threshold
MOS). You gain the degree of freedom of not being hard tied
to substrate (NMOS) or having a huge well-substrate diode
(PMOS) with its capacitance and leakage. You do not see the
back channel MOSFET -if- the S/D are not driven to the bottom
of the "tub" (check that, if thinner than 1um film - FDSOI starts
at ~1000A intrinsic, ~500A "regular" doped, and S/D drive is
any process development team's call).

For -only- RF concerns, maximum frequency for a given gate
lithography, maximum switch linearity, FDSOI all the way.

But if you can stand an octave lower fMax, and want to do
analog as well, need low frequency digital with no "history
effect" on the input buffers and gates, I've come to prefer
PDSOI (as what I relate above is based on hard-knocks
FDSOI product development experience).

praveen450 said:

Can any one tell the difference between floating body SOI CMOS and partially depleted CMOS?. Which configuration is preferred for RFIC Applications?

Click to expand...

Regarding the first question -

Usually, a term "floating body" is used to denote a quasi-neutral (i.e. ionized doping density equal to free carrier density - i.e. semiconductor area is not charged but electrically conductive) region of semiconductor, that does not have a "solid" voltage source applied to it - so that its potential is "floating", i.e. can have different value, depending on circumstances (history, illumination, etc.).
Also, usually, a depleted region in semiconductor (such as a bulk of fully depleted SOI MOSFET) is not referred to as "floating body".
Non-equilibrium carriers captured by floating body (from thermal generation, impact ionization, illumination, etc.) stays there for a long time (~lifetime of carrier - which can be seconds or longer), and changes the potential of the floating body.
To the contrary, non-equilibrium carriers entering the fully depleted body of an SOI MOSFET are immediately extracted to the source due to the built-in electric field.

So, floating body SOI MOSFET is a partially depleted SOI MOSFET that does not have a "body tie" - electrical connection (lateral connection in active silicon) providing a solid, well-defined voltage to the body.

Max