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2 way communication between modules in VHDL

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nizdom

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Hi guys! I just want to ask if two separate modules can interact with each other? It is like, Module A requests Module B to transmit a certain data and then it Module B will transmit it to Module A. In what way is this possible?
 

Hi,

there are many ways..
* serial
* parallel
* shared memory
* FIFO

It depends on may parameters:
* data width
* packet size
* data per packet
* data per second
* how many different commands (requests) with how many parameters...
* build the modules on your own
* decide the protocol on your own
* different clock domains on the modules?

most probably a lot more...

****
As always:
Such a taks begins with specifiactions.
--> This is what you should do first.

Klaus
 

What do you mean by "module" ?
Are both modules on one FPGA ?
 

Yes. both modules are in the same FPGA. They are like separate VHDL files. It's like Module A requests for certain packets from Module B and then depending on this request, Module B will send it to Module A. I am currently working on the code.
 

In that case - I'd use something like ARM's AXI streaming interface. Or Altera's Avalon Streaming which is almost the same thing.
 

What do you mean by "module" ?
Click to expand...
I think the OP means two separate entity blocks.

Use any of the standard bus archs (AHB, AXI4, AXI4Lite, AXI-S, Wishbone, etc) or even you can use your own bus arch. Actually the bus-arch depends on the nature and speed of data to be exchanged.
 

Entity blocks if you are in the land of VHDL
Modules if you are in the land of Verilog

Two names for the same type of structure...a self contained unit of code that does something useful, hopefully, and has a set of inputs and outputs to interface with other such units or other chunks of code.

Regardless, if the OP is in Xilinx land use AXI4 or AXI4-Lite, if they are in Altera land use Avalon, any other vendor just pick something with enough bandwidth and use it.
 

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