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Minus sign for synthesis

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mahmood.n

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It is stated in a book (VHDL for logic synthesis) that

Code: 
5.6.3 Minus Sign
The minus sign is implemented as a 2’s-complement negation. 2’s-complement negation is performed by subtracting the input from zero.

How that is done?! The standard negation is to invert all bits and add 1 to that. Otherwise, doing (0 - 3) to achieve -3 means that the zero has to borrow a number from higher order digit and that is not possible. Isn't that?

Assume we want to calculate -3. That means
Code: 
    000
   -011
  ------


Another question.
In the patterson's book (computer architecture: hardware/software interface) and for dividing signed numbers, it is stated that

Code: 
This anomalous behavior is avoided by following the rule that the dividend and 
remainder must have the same signs, no matter what the signs of the divisor and quotient. 
We calculate the other combinations by following the same rule:
+7 / –2: Quotient = –3, Remainder = +1

Now if you use google to calculate (-1) mod 4, you will get +3 that means (this link)
-1 = -1 * 4 + 3
which contradicts patterson's statement. I also see similar thing in the VHDL book (attachment)



Any idea?
 

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Last edited:

The bit width of the maximum negative number must be within a -2**N to -1 range, therefore -3 can only be represented in 3-bits not 2-bits, as two bits can only represent a -2.
 

OK i edited the post. However, that has no effect on the question.
 

Not sure if this will make complete sense...
Code: 
000
011
101

bit-0:
0-1 borrow: 10-1 = 1
bit-1:
from bit-0 borrowed need to borrow again
borrow for bit-1 10-1 borrow for bit-0: 1-1 = 0
bit-2:
borrow for bit-2 10-0, borrow for bit-1: 1-0 = 1
from this point on all the results will be 1 (sign extending)
 

I think you have to borrow 2 instead of 10.
I also edited the post for another question.
 

It's in binary you can't borrow 2 you can borrow a 1, so that the bit you are subtracting from now represents 10.

There are 10 kinds of people in the world, those who understand binary and those who don't.;-)

- - - Updated - - -

You should stop editing the question, it makes the thread confusing, even to me who has been answering it.

- - - Updated - - -

In the patterson's book (computer architecture: hardware/software interface) and for dividing signed numbers, it is stated that

Code: 
This anomalous behavior is avoided by following the rule that the dividend and 
remainder must have the same signs, no matter what the signs of the divisor and quotient. 
We calculate the other combinations by following the same rule:
+7 / –2: Quotient = –3, Remainder = +1

Now if you use google to calculate (-1) mod 4, you will get +3 that means (this link)
-1 = -1 * 4 + 3
which contradicts patterson's statement. I also see similar thing in the VHDL book (attachment)
Click to expand...
Mod is not the same as division

-1/4 = -025, i.e. the remainder is -1 (= -0.25 * 4)

mod works on a circle 0-1-2-3-0-1-2...
Code: 
0 - 1 - 2 - 3 - 0 - 1 - 2
           -1
            ^ modulo of -1
so if you keep plugging values into google you will see that -2 mod 4 = 2, -3 mod 4 = 1, and -4 mod 4 = 0
 
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