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how to create matrix in VHDL

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nizdom

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Hi guys. I just want to ask, is it possible to create a matrix of 4 columns and 2 rows in VHDL with 4 bits of? how? Also how can I, like assign a variable on the values of the 1st column? thank you.
 

yes it is possible. VHDL supports N-dimensional arrays, or arrays of arrays.
 

can you teach me an example of it's syntax. let's say 4 columns and 2 rows?
 

using VHDL 2008:

Code: 
type matrix_slv_t is array(natural range <>, natural range <>) of std_logic_vector;

...

signal my_matrix : matrix_slv_t(0 to 1, 0 to 3)(3 downto 0);

- - - Updated - - -

with vhdl 93. you need to define the width of the SLV in a constant externally:

Code: 
constant SLV_WIDTH : integer := 4;
type matrix_slv_t is array(natural range <>, natural range <>) of std_logic_vector(SLV_WIDTH-1 downto 0);

...

signal my_matrix : matrix_slv_t(0 to 1, 0 to 3)(3 downto 0);

or just lock it directly into the type.
 

Ah I see. Thanks. How about after placing values on the array or on the cells of the matrix for example, I want to assign a variable to the first column meaning both the values of the two cells under the 1st column. What is it's syntax?
 

How do I place a value on the certain element of the array? What is its syntax?
 

a <= matrix(x,y);

You really need to find a VHDL tutorial or book - this is very basic stuff.
Why not try writing your own code and coming back with problems? it might be better to see what you are actaully doing.
 

matrix array in vhdl

Hello. I want to access a certain element in an array and place a value in it. Can someone help me with its syntax? Here is my array.

Code: 
TYPE VOQ_ROW IS ARRAY (O TO 4) OF STD_LOGIC_VECTOR(3 DOWNTO 0);
TYPE VOQ_MATRIX IS ARRAY(O TO 1) OF VOQ_ROW;
 

Re: matrix array in vhdl

where is your attempt?
 

Can you check this code if it's good in creating a matrix in VHDL?

Code: 
LIBRARY ieee; 
USE ieee.std_logic_1164.all; 
USE ieee.std_logic_unsigned.all; 
ENTITY matrix IS 
    PORT ( 
        RESET_F : IN STD_LOGIC; 
        CLOCK   : IN STD_LOGIC; 
        WRITE   : IN STD_LOGIC; 
        INPUT   : IN STD_LOGIC; 
        ROW     : IN NATURAL RANGE 0 TO 7; 
        COLUMN  : IN NATURAL RANGE 0 TO 7; 
        OUTPUT  : OUT STD_LOGIC 
    ); 
END matrix; 
ARCHITECTURE rtl OF matrix IS 
    TYPE matrix_type IS ARRAY (7 DOWNTO 0) OF 
                        STD_LOGIC_VECTOR(7 DOWNTO 0); 
    SIGNAL current_matrix : matrix_type; 
    SIGNAL next_matrix    :   matrix_type; 
BEGIN 
    OUTPUT <= current_matrix(ROW)(COLUMN); 
    P0 : PROCESS (RESET_F, CLOCK) 
    BEGIN 
        IF (RESET_F = '0') THEN 
            current_matrix <= (others => (others => '0')); 
        ELSIF rising_edge(CLOCK) THEN 
            current_matrix <= next_matrix; 
        END IF; 
    END PROCESS P0; 
    P1 : PROCESS (current_matrix, WRITE, INPUT) 
    BEGIN 
        next_matrix <= current_matrix; 
        IF (WRITE = '1') THEN 
            next_matrix(ROW)(COLUMN) <= INPUT; 
        END IF; 
    END PROCESS P1; 
END rtl;
 

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