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Body substrate effect on PMOS

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VasuRamavel

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what will happen if the body of pmos connected to drain??????
i know threshold of pmos will vary,
but i need to know, in which direction threshold gets varied either it increases or decreases when i connect the body to drain???????
 

Well, if you connect body to the drain in pMOSFET, and apply a negative voltage to drain (with respect to source) - which is a normal operating condition for pMOSFETs - you are applying a negative voltage to the n-type bulk with respect to p+ source.
Thus, you are applying a forward voltage to source-bulk p-n junction (diode).
Then, forget about Vt, all your current will flow through the source/bulk diode, and you transistor will probably burn out.

If your pMOSFET is a symmetric device (source is equivalent to drain), and you use drain as source and source as a drain (applied voltage-wise) - then you are essentially connecting bulk to source, not to drain.

Max
 


It's a Forward Body Bias (FBB) method (threshold decreases), sometimes used in Low Voltage - Very Low Power designs, e.g. SubThreshold Source-Coupled Logic (STSCL) designs, s. e.g. the foll. article by Armin Tajalli and Yusuf Leblebici (2010): View attachment 138780

Hi erikl -

thanks.

Yes, for subthreshold operation, bulk can be shorted with drain (diode is closed).

I thought that in dynamic body biasing, body bias is controlled independently, not by hard connection to drain.
Thanks for bringing this up.

Max
 

I thought that in dynamic body biasing, body bias is controlled independently, not by hard connection to drain.

Hi Max,

It's just one of several Forward Body Bias (FBB) methods, especially practical for very low supply voltage, of course.

Erik
 

Body current is generally not a good thing. It doesn't
always end up entirely where you expect (unless this
is SOI).
 

Right. But if you limit the body forward current far below the operation current (say: nA range, VFBB = 0.2 .. 0.3V), you could still lower the threshold voltage by about this value.
 

thanks for your answers!!!!!!!!!!!! it really helps me a lot!!!!
i want to know how the threshold voltage decreases when bulk is connected to drain of pmos???
and how the leakage current reduces in that condition ??????
 


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