Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] Statement inside CASE in VHDL

Status
Not open for further replies.
D

dzafar

Member level 4
Joined
Jan 17, 2017
Messages
76
Helped
1
Reputation
2
Reaction score
1
Trophy points
8
Activity points
690
Hello there,

My question is are statements inside a 'when' (under case statement) concurrent? i.e. in the image below (shown in red) if I change the order as follows, will the functionality still be the same?

F <= '1';
​
current_state := state1;

Untitled.png

Thanks in advance :)
 

They are effectively concurrent, order does not matter. The two ways you suggest will provide exactly the same result.
 
  • Like
Reactions: dzafar

    D

    dzafar

    Points: 2
    Helpful Answer Positive Rating
As long as the reset value of the state register (which you effectively abstract when using the enumerated type) remains the same - the order doesn't matter.
 

shaiko said:
As long as the reset value of the state register (which you effectively abstract when using the enumerated type) remains the same - the order doesn't matter.
Click to expand...

Only In this case.

The problem here can be an question about the differences between signals and variables.
If everything was a signal, then the order of the assignments is unlikely to make any differences.
But with variables, because they are assigned immediately, changing the code order can significantly affect behaviour.

To the OP: I suggest you stick ONLY with signals for now - variables can cause issues due to code order dependencies.
 
  • Like
Reactions: dzafar

    D

    dzafar

    Points: 2
    Helpful Answer Positive Rating
I suggest only using variables when they do not infer registers.

VHDL often lacks features that would be useful for design, like locally scoped signals.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top