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Hi! May I know if what are the verilog code that are not synthesizable. It can be converted into the generic lib but there are no equivalent cell in my target library. For example:
Hi! May I know if what are the verilog code that are not synthesizable. It can be converted into the generic lib but there are no equivalent cell in my target library. For example:
I see some poorly coded verilog, but it should synthesize. Library presence or lack of doesn't determine what portions of the verilog language can be understood by a compiler. I believe you are targetting the wrong solution if you are thinking of a library issue. Or you are talking about mapping instead of compilation, but that is a different problem for sure.
Potential causes could be:
- Wrong target library read in
- Library without a async reset FF
- Library has async reset FF, but it was set as dont_used cell
- Scripts or other issue before compile
What else ( warning/error ) did you see in the log file ?
Yes I am talking about mapping it into my technology file. I have already read the datasheet of my library, it contains no async reset FF. What do I need to do? is it to make a new standard cell library or to revise my RTL code?
Yes I am talking about mapping it into my technology file. I have already read the datasheet of my library, it contains no async reset FF. What do I need to do? is it to make a new standard cell library or to revise my RTL code?
Making a new library adding new cells is not our designing task. Let confirm with your manager or related people who can design with/without asyn reset FF.
Then, you can ask for library vendor to update, or change your design according to library support.
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